Jakob Stoklund Olesen 243296690e Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl(). ... The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97262 91177308-0d34-0410-b5e6-96231b3b80d8		2010-02-26 21:09:24 +00:00
..
Alpha
ARM	Check for comparisons of +/- zero when optimizing less-than-or-equal and	2010-02-24 22:15:53 +00:00
Blackfin	Change the scheduler from adding nodes in allnodes order	2010-02-24 06:11:37 +00:00
CBackend
CellSPU
CPP
Generic
MBlaze	Adding the MicroBlaze backend.	2010-02-23 19:15:24 +00:00
Mips
MSP430	Change the scheduler from adding nodes in allnodes order	2010-02-24 06:11:37 +00:00
PIC16	Reapply things reverted back in 97220, with the fixed test case.	2010-02-26 17:59:28 +00:00
PowerPC	Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl().	2010-02-26 21:09:24 +00:00
SPARC
SystemZ
Thumb
Thumb2	Create a stack frame on ARM when	2010-02-24 22:43:17 +00:00
X86	change the scope node to include a list of children to be checked	2010-02-25 19:00:39 +00:00
XCore	Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.	2010-02-26 16:44:51 +00:00