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https://github.com/c64scene-ar/llvm-6502.git
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2c2c33a167
Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
1.8 KiB
LLVM
74 lines
1.8 KiB
LLVM
; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=32
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; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
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; RUN: llc -march=mips -mcpu=mips16 < %s
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; 32: madd ${{[0-9]+}}
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; DSP: madd $ac
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define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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%conv2 = sext i32 %b to i64
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%mul = mul nsw i64 %conv2, %conv
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%conv4 = sext i32 %c to i64
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%add = add nsw i64 %mul, %conv4
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ret i64 %add
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}
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; 32: maddu ${{[0-9]+}}
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; DSP: maddu $ac
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define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = zext i32 %a to i64
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%conv2 = zext i32 %b to i64
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%mul = mul nsw i64 %conv2, %conv
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%conv4 = zext i32 %c to i64
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%add = add nsw i64 %mul, %conv4
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ret i64 %add
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}
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; 32: madd ${{[0-9]+}}
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; DSP: madd $ac
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define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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%conv2 = sext i32 %b to i64
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%mul = mul nsw i64 %conv2, %conv
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%add = add nsw i64 %mul, %c
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ret i64 %add
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}
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; 32: msub ${{[0-9]+}}
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; DSP: msub $ac
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define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = sext i32 %c to i64
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%conv2 = sext i32 %a to i64
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%conv4 = sext i32 %b to i64
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%mul = mul nsw i64 %conv4, %conv2
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%sub = sub nsw i64 %conv, %mul
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ret i64 %sub
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}
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; 32: msubu ${{[0-9]+}}
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; DSP: msubu $ac
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define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%conv = zext i32 %c to i64
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%conv2 = zext i32 %a to i64
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%conv4 = zext i32 %b to i64
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%mul = mul nsw i64 %conv4, %conv2
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%sub = sub nsw i64 %conv, %mul
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ret i64 %sub
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}
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; 32: msub ${{[0-9]+}}
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; DSP: msub $ac
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define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {
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entry:
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%conv = sext i32 %a to i64
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%conv3 = sext i32 %b to i64
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%mul = mul nsw i64 %conv3, %conv
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%sub = sub nsw i64 %c, %mul
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ret i64 %sub
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}
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