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https://github.com/c64scene-ar/llvm-6502.git
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47b92f3d83
"With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144414 91177308-0d34-0410-b5e6-96231b3b80d8
250 lines
9.0 KiB
C++
250 lines
9.0 KiB
C++
//===-- MipsMCCodeEmitter.cpp - Convert Mips code to machine code ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MipsMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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//
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#define DEBUG_TYPE "mccodeemitter"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MCTargetDesc/MipsFixupKinds.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class MipsMCCodeEmitter : public MCCodeEmitter {
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MipsMCCodeEmitter(const MipsMCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const MipsMCCodeEmitter &); // DO NOT IMPLEMENT
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const MCInstrInfo &MCII;
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const MCSubtargetInfo &STI;
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MCContext &Ctx;
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public:
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MipsMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
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MCContext &ctx) : MCII(mcii), STI(sti) , Ctx(ctx) {}
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~MipsMCCodeEmitter() {}
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void EmitByte(unsigned char C, raw_ostream &OS) const {
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OS << (char)C;
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}
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void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
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// Output the instruction encoding in little endian byte order.
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, OS);
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Val >>= 8;
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}
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}
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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unsigned getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBranchJumpOpValue - Return binary encoding of the jump
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// target operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBranchTargetOpValue - Return binary encoding of the branch
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// target operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getMachineOpValue - Return binary encoding of operand. If the machin
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// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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}; // class MipsMCCodeEmitter
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} // namespace
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MCCodeEmitter *llvm::createMipsMCCodeEmitter(const MCInstrInfo &MCII,
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const MCSubtargetInfo &STI,
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MCContext &Ctx)
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{
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return new MipsMCCodeEmitter(MCII, STI, Ctx);
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}
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/// EncodeInstruction - Emit the instruction.
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/// Size the instruction (currently only 4 bytes
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void MipsMCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const
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{
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uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
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// Check for unimplemented opcodes.
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// Unfortunately in MIPS both NOT and SLL will come in with Binary == 0
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// so we have to special check for them.
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unsigned Opcode = MI.getOpcode();
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if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
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llvm_unreachable("unimplemented opcode in EncodeInstruction()");
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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uint64_t TSFlags = Desc.TSFlags;
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// Pseudo instructions don't get encoded and shouldn't be here
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// in the first place!
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if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo)
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llvm_unreachable("Pseudo opcode found in EncodeInstruction()");
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// For now all instructions are 4 bytes
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int Size = 4; // FIXME: Have Desc.getSize() return the correct value!
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EmitInstruction(Binary, Size, OS);
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}
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/// getBranchTargetOpValue - Return binary encoding of the branch
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isExpr() && "getBranchTargetOpValue expects only expressions");
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const MCExpr *Expr = MO.getExpr();
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Fixups.push_back(MCFixup::Create(0, Expr,
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MCFixupKind(Mips::fixup_Mips_PC16)));
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return 0;
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}
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/// getJumpTargetOpValue - Return binary encoding of the jump
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isExpr() && "getJumpTargetOpValue expects only expressions");
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const MCExpr *Expr = MO.getExpr();
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Fixups.push_back(MCFixup::Create(0, Expr,
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MCFixupKind(Mips::fixup_Mips_26)));
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return 0;
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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unsigned Reg = MO.getReg();
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unsigned RegNo = getMipsRegisterNumbering(Reg);
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return RegNo;
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} else if (MO.isImm()) {
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return static_cast<unsigned>(MO.getImm());
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} else if (MO.isFPImm()) {
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return static_cast<unsigned>(APFloat(MO.getFPImm())
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.bitcastToAPInt().getHiBits(32).getLimitedValue());
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} else if (MO.isExpr()) {
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const MCExpr *Expr = MO.getExpr();
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MCExpr::ExprKind Kind = Expr->getKind();
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if (Kind == MCExpr::SymbolRef) {
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Mips::Fixups FixupKind = Mips::fixup_Mips_NONE;
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MCSymbolRefExpr::VariantKind SymRefKind =
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cast<MCSymbolRefExpr>(Expr)->getKind();
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switch(SymRefKind) {
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case MCSymbolRefExpr::VK_Mips_GPREL:
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FixupKind = Mips::fixup_Mips_GPREL16;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT_CALL:
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FixupKind = Mips::fixup_Mips_CALL16;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT:
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FixupKind = Mips::fixup_Mips_GOT16;
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break;
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case MCSymbolRefExpr::VK_Mips_ABS_HI:
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FixupKind = Mips::fixup_Mips_HI16;
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break;
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case MCSymbolRefExpr::VK_Mips_ABS_LO:
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FixupKind = Mips::fixup_Mips_LO16;
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break;
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case MCSymbolRefExpr::VK_Mips_TLSGD:
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FixupKind = Mips::fixup_Mips_TLSGD;
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break;
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case MCSymbolRefExpr::VK_Mips_GOTTPREL:
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FixupKind = Mips::fixup_Mips_GOTTPREL;
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break;
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case MCSymbolRefExpr::VK_Mips_TPREL_HI:
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FixupKind = Mips::fixup_Mips_TPREL_HI;
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break;
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case MCSymbolRefExpr::VK_Mips_TPREL_LO:
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FixupKind = Mips::fixup_Mips_TPREL_LO;
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break;
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default:
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return 0;
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} // switch
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Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
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} // if SymbolRef
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// All of the information is in the fixup.
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return 0;
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}
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llvm_unreachable("Unable to encode MCOperand!");
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// Not reached
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return 0;
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}
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/// getMemEncoding - Return binary encoding of memory related operand.
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/// If the offset operand requires relocation, record the relocation.
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unsigned
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MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
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assert(MI.getOperand(OpNo).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
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unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
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return (OffBits & 0xFFFF) | RegBits;
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}
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unsigned
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MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// FIXME: implement
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return 0;
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}
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unsigned
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MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// FIXME: implement
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return 0;
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}
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#include "MipsGenMCCodeEmitter.inc"
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