Justin Holewinski 49683f3c96 This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. ... The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8		2012-05-04 20:18:50 +00:00
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ARM	Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs.	2012-05-02 22:17:40 +00:00
CellSPU	Flip the new block-placement pass to be on by default.	2012-04-16 13:49:17 +00:00
CPP
Generic	Move to X86 directory because this fails on non-X86 platforms.	2012-04-16 16:38:48 +00:00
Hexagon	Support for target dependent Hexagon VLIW packetizer.	2012-05-03 21:52:53 +00:00
MBlaze
Mips	Do not use $gp as a dedicated global register if the target ABI is not O32.	2012-04-25 01:24:52 +00:00
MSP430
NVPTX	This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.	2012-05-04 20:18:50 +00:00
PowerPC	Remove dead SD nodes after the combining pass. Fixes PR12201.	2012-04-16 03:33:22 +00:00
PTX
SPARC	Regression test for PR2960.	2012-05-01 11:11:34 +00:00
Thumb	Make test less fragile.	2012-04-27 20:48:18 +00:00
Thumb2	Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions.	2012-05-04 19:53:56 +00:00
X86	Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.	2012-05-04 04:44:49 +00:00
XCore	Flip the new block-placement pass to be on by default.	2012-04-16 13:49:17 +00:00