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4969310052
This required disabling a PowerPC optimization that did the following: input: x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16> lowered to: tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8> x = ADD tmp, tmp The add now gets folded immediately and we're back at the BUILD_VECTOR we started from. I don't see a way to fix this currently so I left it disabled for now. Fix some trivially foldable X86 tests too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174325 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
1.2 KiB
LLVM
40 lines
1.2 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse41 | FileCheck %s
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; In this test we check that sign-extend of the mask bit is performed by
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; shifting the needed bit to the MSB, and not using shl+sra.
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;CHECK: vsel_float
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;CHECK: movl $-2147483648
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;CHECK-NEXT: movd
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;CHECK-NEXT: blendvps
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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}
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;CHECK: vsel_4xi8
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;CHECK: movl $-2147483648
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;CHECK-NEXT: movd
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;CHECK-NEXT: blendvps
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;CHECK: ret
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define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2
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ret <4 x i8> %vsel
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}
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; We do not have native support for v8i16 blends and we have to use the
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; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not r
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; reduce the mask in this case.
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;CHECK: vsel_8xi16
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;CHECK: psllw
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;CHECK-NOT: psraw
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;CHECK: pblendvb
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;CHECK: ret
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define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2
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ret <8 x i16> %vsel
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}
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