mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0fd57f4b56
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207510 91177308-0d34-0410-b5e6-96231b3b80d8
183 lines
6.7 KiB
C++
183 lines
6.7 KiB
C++
//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an AArch64 MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_AARCH64INSTPRINTER_H
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#define LLVM_AARCH64INSTPRINTER_H
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace llvm {
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class MCOperand;
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class AArch64InstPrinter : public MCInstPrinter {
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public:
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AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
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// Autogenerated by tblgen
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void printInstruction(const MCInst *MI, raw_ostream &O);
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bool printAliasInstr(const MCInst *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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static const char *getInstructionName(unsigned Opcode);
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void printRegName(raw_ostream &O, unsigned RegNum) const override;
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template<unsigned MemSize, unsigned RmSize>
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void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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printAddrRegExtendOperand(MI, OpNum, O, MemSize, RmSize);
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}
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void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O, unsigned MemSize,
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unsigned RmSize);
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void printAddSubImmLSL0Operand(const MCInst *MI,
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unsigned OpNum, raw_ostream &O);
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void printAddSubImmLSL12Operand(const MCInst *MI,
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unsigned OpNum, raw_ostream &O);
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void printBareImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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template<unsigned RegWidth>
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void printBFILSBOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printBFIWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printBFXWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printCondCodeOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printCRxOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printCVTFixedPosOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
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void printFPZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
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template<int MemScale>
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void printOffsetUImm12Operand(const MCInst *MI,
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unsigned OpNum, raw_ostream &o) {
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printOffsetUImm12Operand(MI, OpNum, o, MemScale);
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}
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void printOffsetUImm12Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &o, int MemScale);
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template<unsigned field_width, unsigned scale>
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void printLabelOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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template<unsigned RegWidth>
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void printLogicalImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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template<typename SomeNamedImmMapper>
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void printNamedImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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printNamedImmOperand(SomeNamedImmMapper(), MI, OpNum, O);
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}
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void printNamedImmOperand(const NamedImmMapper &Mapper,
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const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
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const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printMRSOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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printSysRegOperand(A64SysReg::MRSMapper(), MI, OpNum, O);
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}
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void printMSROperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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printSysRegOperand(A64SysReg::MSRMapper(), MI, OpNum, O);
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}
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void printShiftOperand(const char *name, const MCInst *MI,
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unsigned OpIdx, raw_ostream &O);
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void printLSLOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printLSROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printShiftOperand("lsr", MI, OpNum, O);
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}
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void printASROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printShiftOperand("asr", MI, OpNum, O);
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}
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void printROROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printShiftOperand("ror", MI, OpNum, O);
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}
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template<A64SE::ShiftExtSpecifiers Shift>
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void printShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printShiftOperand(MI, OpNum, O, Shift);
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}
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void printShiftOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O, A64SE::ShiftExtSpecifiers Sh);
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void printMoveWideImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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template<int MemSize> void
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printSImm7ScaledOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printOffsetSImm9Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printPRFMOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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template<A64SE::ShiftExtSpecifiers EXT>
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void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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printRegExtendOperand(MI, OpNum, O, EXT);
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}
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void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O, A64SE::ShiftExtSpecifiers Ext);
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void printVPRRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
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bool isStackReg(unsigned RegNo) {
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return RegNo == AArch64::XSP || RegNo == AArch64::WSP;
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}
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template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
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void printNeonMovImmShiftOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printNeonUImm0Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printUImmHexOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printUImmBareOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printNeonUImm64MaskOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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template <A64Layout::VectorLayout Layout, unsigned Count>
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void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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};
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}
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#endif
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