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https://github.com/c64scene-ar/llvm-6502.git
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22f779d1fd
This patch implements the infrastructure to use named register constructs in programs that need access to specific registers (bare metal, kernels, etc). So far, only the stack pointer is supported as a technology preview, but as it is, the intrinsic can already support all non-allocatable registers from any architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208104 91177308-0d34-0410-b5e6-96231b3b80d8
430 lines
15 KiB
C++
430 lines
15 KiB
C++
//==-- ARM64ISelLowering.h - ARM64 DAG Lowering Interface --------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that ARM64 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_ARM64_ISELLOWERING_H
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#define LLVM_TARGET_ARM64_ISELLOWERING_H
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace ARM64ISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
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CALL, // Function call.
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// Almost the same as a normal call node, except that a TLSDesc relocation is
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// needed so the linker can relax it correctly if possible.
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TLSDESC_CALL,
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ADRP, // Page address of a TargetGlobalAddress operand.
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ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
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LOADgot, // Load from automatically generated descriptor (e.g. Global
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// Offset Table, TLS record).
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RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
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BRCOND, // Conditional branch instruction; "b.cond".
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CSEL,
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FCSEL, // Conditional move instruction.
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CSINV, // Conditional select invert.
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CSNEG, // Conditional select negate.
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CSINC, // Conditional select increment.
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// Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
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// ELF.
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THREAD_POINTER,
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ADC,
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SBC, // adc, sbc instructions
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// Arithmetic instructions which write flags.
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ADDS,
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SUBS,
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ADCS,
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SBCS,
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ANDS,
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// Floating point comparison
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FCMP,
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// Floating point max and min instructions.
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FMAX,
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FMIN,
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// Scalar extract
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EXTR,
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// Scalar-to-vector duplication
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DUP,
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DUPLANE8,
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DUPLANE16,
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DUPLANE32,
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DUPLANE64,
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// Vector immedate moves
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MOVI,
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MOVIshift,
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MOVIedit,
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MOVImsl,
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FMOV,
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MVNIshift,
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MVNImsl,
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// Vector immediate ops
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BICi,
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ORRi,
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// Vector bit select: similar to ISD::VSELECT but not all bits within an
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// element must be identical.
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BSL,
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// Vector arithmetic negation
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NEG,
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// Vector shuffles
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ZIP1,
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ZIP2,
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UZP1,
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UZP2,
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TRN1,
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TRN2,
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REV16,
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REV32,
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REV64,
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EXT,
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// Vector shift by scalar
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VSHL,
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VLSHR,
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VASHR,
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// Vector shift by scalar (again)
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SQSHL_I,
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UQSHL_I,
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SQSHLU_I,
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SRSHR_I,
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URSHR_I,
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// Vector comparisons
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CMEQ,
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CMGE,
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CMGT,
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CMHI,
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CMHS,
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FCMEQ,
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FCMGE,
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FCMGT,
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// Vector zero comparisons
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CMEQz,
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CMGEz,
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CMGTz,
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CMLEz,
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CMLTz,
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FCMEQz,
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FCMGEz,
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FCMGTz,
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FCMLEz,
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FCMLTz,
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// Vector bitwise negation
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NOT,
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// Vector bitwise selection
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BIT,
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// Compare-and-branch
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CBZ,
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CBNZ,
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TBZ,
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TBNZ,
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// Tail calls
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TC_RETURN,
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// Custom prefetch handling
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PREFETCH,
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// {s|u}int to FP within a FP register.
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SITOF,
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UITOF
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};
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} // end namespace ARM64ISD
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class ARM64Subtarget;
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class ARM64TargetMachine;
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class ARM64TargetLowering : public TargetLowering {
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bool RequireStrictAlign;
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public:
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explicit ARM64TargetLowering(ARM64TargetMachine &TM);
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/// Selects the correct CCAssignFn for a the given CallingConvention
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/// value.
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CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
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/// computeMaskedBitsForTargetNode - Determine which of the bits specified in
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/// Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero,
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APInt &KnownOne, const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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MVT getScalarShiftAmountTy(EVT LHSTy) const override;
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/// allowsUnalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses. of the specified type.
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bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
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bool *Fast = nullptr) const override {
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if (RequireStrictAlign)
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return false;
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// FIXME: True for Cyclone, but not necessary others.
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if (Fast)
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*Fast = true;
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return true;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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unsigned getFunctionAlignment(const Function *F) const;
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/// getMaximalGlobalOffset - Returns the maximal possible offset which can
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/// be used for loads / stores from the global.
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unsigned getMaximalGlobalOffset() const override;
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/// Returns true if a cast between SrcAS and DestAS is a noop.
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
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// Addrspacecasts are always noops.
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return true;
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}
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/// createFastISel - This method returns a target specific FastISel object,
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/// or null if the target does not support "fast" ISel.
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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/// isShuffleMaskLegal - Return true if the given shuffle mask can be
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/// codegen'd directly, or if it should be stack expanded.
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
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SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
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MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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unsigned Intrinsic) const override;
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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bool isTruncateFree(EVT VT1, EVT VT2) const override;
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bool isZExtFree(Type *Ty1, Type *Ty2) const override;
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bool isZExtFree(EVT VT1, EVT VT2) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool hasPairedLoad(Type *LoadedType,
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unsigned &RequiredAligment) const override;
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bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
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bool isLegalAddImmediate(int64_t) const override;
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bool isLegalICmpImmediate(int64_t) const override;
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
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/// \brief Return the cost of the scaling factor used in the addressing
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/// mode represented by AM for this target, for a load/store
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/// of the specified type.
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/// If the AM is supported, the return value must be >= 0.
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/// If the AM is not supported, it returns a negative value.
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int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
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/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
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/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
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/// expanded to FMAs when this method returns true, otherwise fmuladd is
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/// expanded to fmul + fadd.
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bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
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/// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
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bool isDesirableToCommuteWithShift(const SDNode *N) const override;
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/// \brief Returns true if it is beneficial to convert a load of a constant
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/// to just the constant itself.
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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AtomicOrdering Ord) const override;
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Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
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Value *Addr, AtomicOrdering Ord) const override;
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bool shouldExpandAtomicInIR(Instruction *Inst) const override;
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private:
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/// Subtarget - Keep a pointer to the ARM64Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARM64Subtarget *Subtarget;
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void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
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void addDRTypeForNEON(MVT VT);
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void addQRTypeForNEON(MVT VT);
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SDValue
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(CallLoweringInfo & /*CLI*/,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
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bool isThisReturn, SDValue ThisVal) const;
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bool isEligibleForTailCallOptimization(
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SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
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bool isCalleeStructRet, bool isCallerStructRet,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
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void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
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SDValue &Chain) const;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
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SelectionDAG &DAG) const override;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerELFTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
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SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
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RTLIB::Libcall Call) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
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ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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unsigned getRegisterByName(const char* RegName) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight
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getSingleConstraintMatchWeight(AsmOperandInfo &info,
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const char *constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const override;
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
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bool mayBeEmittedAsTailCall(CallInst *CI) const override;
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bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM, bool &IsInc,
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SelectionDAG &DAG) const;
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bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
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SDValue &Offset, ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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};
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namespace ARM64 {
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo);
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} // end namespace ARM64
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} // end namespace llvm
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#endif // LLVM_TARGET_ARM64_ISELLOWERING_H
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