Bill Schmidt 49b3971b70 [PowerPC] Fix reverted patch r227976 to avoid register assignment issues ... See full discussion in http://reviews.llvm.org/D7491. We now hide the add-immediate and call instructions together in a separate pseudo-op, which is tagged to define GPR3 and clobber the call-killed registers. The PPCTLSDynamicCall pass prior to RA now expands this op into the two separate addi and call ops, with explicit definitions of GPR3 on both instructions, and explicit clobbers on the call instruction. The pass is now marked as requiring and preserving the LiveIntervals and SlotIndexes analyses, and fixes these up after the replacement sequences are introduced. Self-hosting has been verified on LE P8 and BE P7 with various optimization levels, etc. It has also been verified with the --no-tls-optimize flag workaround removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228725 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-10 19:09:05 +00:00
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AArch64	ARM & AArch64: teach LowerVSETCC that output type size may differ from input.	2015-02-08 00:50:47 +00:00
ARM	[ARM] Add armv6s[-]m as an alias to armv6[-]m	2015-02-10 15:15:08 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Factoring classes out of store patterns.	2015-02-09 20:33:46 +00:00
Inputs
Mips
MSP430
NVPTX
PowerPC	[PowerPC] Fix reverted patch r227976 to avoid register assignment issues	2015-02-10 19:09:05 +00:00
R600	R600/SI: Amend a test to ensure WQM is enabled for LDS in pixel shaders	2015-02-06 02:51:29 +00:00
SPARC
SystemZ	Use the integrated assembler as default on SystemZ	2015-01-13 19:45:16 +00:00
Thumb
Thumb2
X86	X86: Emit Win64 SaveXMM opcodes at the right offset in the right order	2015-02-10 19:01:47 +00:00
XCore