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https://github.com/c64scene-ar/llvm-6502.git
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up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
336 lines
11 KiB
C++
336 lines
11 KiB
C++
//===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to Cell SPU assembly language. This printer
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// is the output mechanism used by `llc'.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asmprinter"
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#include "SPU.h"
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#include "SPUTargetMachine.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class SPUAsmPrinter : public AsmPrinter {
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public:
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explicit SPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) :
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AsmPrinter(TM, Streamer) {}
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virtual const char *getPassName() const {
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return "STI CBEA SPU Assembly Printer";
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}
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description.
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void printInstruction(const MachineInstr *MI, raw_ostream &OS);
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static const char *getRegisterName(unsigned RegNo);
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void EmitInstruction(const MachineInstr *MI) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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printInstruction(MI, OS);
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OutStreamer.EmitRawText(OS.str());
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}
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void printOp(const MachineOperand &MO, raw_ostream &OS);
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void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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if (MO.isReg()) {
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O << getRegisterName(MO.getReg());
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} else if (MO.isImm()) {
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O << MO.getImm();
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} else {
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printOp(MO, O);
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}
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}
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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void
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printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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unsigned int value = MI->getOperand(OpNo).getImm();
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assert(value < (1 << 8) && "Invalid u7 argument");
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O << value;
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}
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void
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printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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char value = MI->getOperand(OpNo).getImm();
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O << (int) value;
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O << "(";
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printOperand(MI, OpNo+1, O);
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O << ")";
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}
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void
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printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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O << (short) MI->getOperand(OpNo).getImm();
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}
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void
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printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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O << (unsigned short)MI->getOperand(OpNo).getImm();
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}
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void
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printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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// When used as the base register, r0 reads constant zero rather than
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// the value contained in the register. For this reason, the darwin
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// assembler requires that we print r0 as 0 (no r) when used as the base.
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const MachineOperand &MO = MI->getOperand(OpNo);
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O << getRegisterName(MO.getReg()) << ", ";
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printOperand(MI, OpNo+1, O);
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}
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void
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printU18ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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unsigned int value = MI->getOperand(OpNo).getImm();
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assert(value <= (1 << 19) - 1 && "Invalid u18 argument");
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O << value;
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}
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void
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printS10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
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>> 16);
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assert((value >= -(1 << 9) && value <= (1 << 9) - 1)
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&& "Invalid s10 argument");
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O << value;
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}
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void
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printU10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
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>> 16);
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assert((value <= (1 << 10) - 1) && "Invalid u10 argument");
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O << value;
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}
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void
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printDFormAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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assert(MI->getOperand(OpNo).isImm() &&
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"printDFormAddr first operand is not immediate");
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int64_t value = int64_t(MI->getOperand(OpNo).getImm());
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int16_t value16 = int16_t(value);
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assert((value16 >= -(1 << (9+4)) && value16 <= (1 << (9+4)) - 1)
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&& "Invalid dform s10 offset argument");
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O << (value16 & ~0xf) << "(";
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printOperand(MI, OpNo+1, O);
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O << ")";
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}
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void
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printAddr256K(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
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{
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/* Note: operand 1 is an offset or symbol name. */
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if (MI->getOperand(OpNo).isImm()) {
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printS16ImmOperand(MI, OpNo, O);
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} else {
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printOp(MI->getOperand(OpNo), O);
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if (MI->getOperand(OpNo+1).isImm()) {
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int displ = int(MI->getOperand(OpNo+1).getImm());
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if (displ > 0)
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O << "+" << displ;
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else if (displ < 0)
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O << displ;
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}
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}
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}
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void printCallOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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printOp(MI->getOperand(OpNo), O);
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}
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void printHBROperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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printOp(MI->getOperand(OpNo), O);
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}
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void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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// Used to generate a ".-<target>", but it turns out that the assembler
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// really wants the target.
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//
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// N.B.: This operand is used for call targets. Branch hints are another
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// animal entirely.
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printOp(MI->getOperand(OpNo), O);
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}
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void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm()) {
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printS16ImmOperand(MI, OpNo, O);
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} else {
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printOp(MI->getOperand(OpNo), O);
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O << "@h";
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}
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}
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void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm()) {
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printS16ImmOperand(MI, OpNo, O);
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} else {
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printOp(MI->getOperand(OpNo), O);
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O << "@l";
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}
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}
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/// Print local store address
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void printSymbolLSA(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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printOp(MI->getOperand(OpNo), O);
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}
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void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm()) {
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int value = (int) MI->getOperand(OpNo).getImm();
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assert((value >= 0 && value < 16)
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&& "Invalid negated immediate rotate 7-bit argument");
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O << -value;
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} else {
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llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
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}
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}
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void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O){
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assert(MI->getOperand(OpNo).isImm() &&
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"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
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int value = (int) MI->getOperand(OpNo).getImm();
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assert((value >= 0 && value <= 32)
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&& "Invalid negated immediate rotate 7-bit argument");
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O << -value;
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}
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};
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} // end of anonymous namespace
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// Include the auto-generated portion of the assembly writer
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#include "SPUGenAsmWriter.inc"
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void SPUAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
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switch (MO.getType()) {
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case MachineOperand::MO_Immediate:
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report_fatal_error("printOp() does not handle immediate values");
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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return;
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case MachineOperand::MO_JumpTableIndex:
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O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
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<< '_' << MO.getIndex();
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return;
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case MachineOperand::MO_ConstantPoolIndex:
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O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
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<< '_' << MO.getIndex();
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return;
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case MachineOperand::MO_ExternalSymbol:
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// Computing the address of an external symbol, not calling it.
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if (TM.getRelocationModel() != Reloc::Static) {
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O << "L" << MAI->getGlobalPrefix() << MO.getSymbolName()
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<< "$non_lazy_ptr";
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return;
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}
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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return;
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case MachineOperand::MO_GlobalAddress:
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// External or weakly linked global variables need non-lazily-resolved
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// stubs
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if (TM.getRelocationModel() != Reloc::Static) {
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const GlobalValue *GV = MO.getGlobal();
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if (((GV->isDeclaration() || GV->hasWeakLinkage() ||
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GV->hasLinkOnceLinkage() || GV->hasCommonLinkage()))) {
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O << *GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
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return;
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}
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}
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O << *Mang->getSymbol(MO.getGlobal());
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return;
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case MachineOperand::MO_MCSymbol:
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O << *(MO.getMCSymbol());
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return;
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default:
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O << "<unknown operand type: " << MO.getType() << ">";
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return;
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}
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}
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/// PrintAsmOperand - Print out an operand for an inline asm expression.
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///
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bool SPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode, raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0) return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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default:
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// See if this is a generic print operand
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return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
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case 'L': // Write second word of DImode reference.
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// Verify that this operand has two consecutive registers.
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if (!MI->getOperand(OpNo).isReg() ||
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OpNo+1 == MI->getNumOperands() ||
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!MI->getOperand(OpNo+1).isReg())
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return true;
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++OpNo; // Return the high-part.
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break;
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}
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}
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printOperand(MI, OpNo, O);
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return false;
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}
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bool SPUAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo, unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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printMemRegReg(MI, OpNo, O);
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return false;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeCellSPUAsmPrinter() {
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RegisterAsmPrinter<SPUAsmPrinter> X(TheCellSPUTarget);
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}
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