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and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
433 lines
17 KiB
C++
433 lines
17 KiB
C++
//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the ScheduleDAGInstrs class, which implements re-scheduling
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// of MachineInstrs.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched-instrs"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtarget.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/SmallSet.h"
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#include <map>
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using namespace llvm;
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namespace {
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class VISIBILITY_HIDDEN LoopDependencies {
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const MachineLoopInfo &MLI;
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const MachineDominatorTree &MDT;
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public:
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typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
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LoopDeps;
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LoopDeps Deps;
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LoopDependencies(const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt) :
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MLI(mli), MDT(mdt) {}
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void VisitLoop(const MachineLoop *Loop) {
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Deps.clear();
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MachineBasicBlock *Header = Loop->getHeader();
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SmallSet<unsigned, 8> LoopLiveIns;
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for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
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LE = Header->livein_end(); LI != LE; ++LI)
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LoopLiveIns.insert(*LI);
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const MachineDomTreeNode *Node = MDT.getNode(Header);
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const MachineBasicBlock *MBB = Node->getBlock();
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assert(Loop->contains(MBB) &&
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"Loop does not contain header!");
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VisitRegion(Node, MBB, Loop, LoopLiveIns);
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}
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private:
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void VisitRegion(const MachineDomTreeNode *Node,
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const MachineBasicBlock *MBB,
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const MachineLoop *Loop,
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const SmallSet<unsigned, 8> &LoopLiveIns) {
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unsigned Count = 0;
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I, ++Count) {
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const MachineInstr *MI = I;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned MOReg = MO.getReg();
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if (LoopLiveIns.count(MOReg))
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Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
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}
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}
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const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
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for (std::vector<MachineDomTreeNode*>::const_iterator I =
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Children.begin(), E = Children.end(); I != E; ++I) {
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const MachineDomTreeNode *ChildNode = *I;
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MachineBasicBlock *ChildBlock = ChildNode->getBlock();
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if (Loop->contains(ChildBlock))
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VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
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}
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}
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};
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}
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt)
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: ScheduleDAG(mf), MLI(mli), MDT(mdt) {}
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void ScheduleDAGInstrs::BuildSchedGraph() {
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SUnits.reserve(BB->size());
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// We build scheduling units by walking a block's instruction list from bottom
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// to top.
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// Remember where a generic side-effecting instruction is as we procede. If
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// ChainMMO is null, this is assumed to have arbitrary side-effects. If
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// ChainMMO is non-null, then Chain makes only a single memory reference.
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SUnit *Chain = 0;
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MachineMemOperand *ChainMMO = 0;
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// Memory references to specific known memory locations are tracked so that
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// they can be given more precise dependencies.
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std::map<const Value *, SUnit *> MemDefs;
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std::map<const Value *, std::vector<SUnit *> > MemUses;
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// Terminators can perform control transfers, we we need to make sure that
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// all the work of the block is done before the terminator.
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SUnit *Terminator = 0;
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LoopDependencies LoopRegs(MLI, MDT);
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// Track which regs are live into a loop, to help guide back-edge-aware
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// scheduling.
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SmallSet<unsigned, 8> LoopLiveInRegs;
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if (MachineLoop *ML = MLI.getLoopFor(BB))
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if (BB == ML->getLoopLatch()) {
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MachineBasicBlock *Header = ML->getHeader();
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for (MachineBasicBlock::livein_iterator I = Header->livein_begin(),
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E = Header->livein_end(); I != E; ++I)
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LoopLiveInRegs.insert(*I);
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LoopRegs.VisitLoop(ML);
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}
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// Check to see if the scheduler cares about latencies.
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bool UnitLatencies = ForceUnitLatencies();
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// Ask the target if address-backscheduling is desirable, and if so how much.
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unsigned SpecialAddressLatency =
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TM.getSubtarget<TargetSubtarget>().getSpecialAddressLatency();
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for (MachineBasicBlock::iterator MII = BB->end(), MIE = BB->begin();
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MII != MIE; --MII) {
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MachineInstr *MI = prior(MII);
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const TargetInstrDesc &TID = MI->getDesc();
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SUnit *SU = NewSUnit(MI);
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// Assign the Latency field of SU using target-provided information.
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if (UnitLatencies)
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SU->Latency = 1;
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else
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ComputeLatency(SU);
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// Add register-based dependencies (data, anti, and output).
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for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
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std::vector<SUnit *> &UseList = Uses[Reg];
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std::vector<SUnit *> &DefList = Defs[Reg];
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// Optionally add output and anti dependencies.
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// TODO: Using a latency of 1 here assumes there's no cost for
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// reusing registers.
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SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
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for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
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SUnit *DefSU = DefList[i];
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if (DefSU != SU &&
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(Reg)))
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DefSU->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/Reg));
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}
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &DefList = Defs[*Alias];
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for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
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SUnit *DefSU = DefList[i];
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if (DefSU != SU &&
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(Kind != SDep::Output || !MO.isDead() ||
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!DefSU->getInstr()->registerDefIsDead(Reg)))
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DefSU->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/ *Alias));
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}
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}
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if (MO.isDef()) {
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// Add any data dependencies.
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unsigned DataLatency = SU->Latency;
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU != SU) {
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unsigned LDataLatency = DataLatency;
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// Optionally add in a special extra latency for nodes that
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// feed addresses.
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// TODO: Do this for register aliases too.
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if (SpecialAddressLatency != 0 && !UnitLatencies) {
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MachineInstr *UseMI = UseSU->getInstr();
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const TargetInstrDesc &UseTID = UseMI->getDesc();
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int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
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assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
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if ((UseTID.mayLoad() || UseTID.mayStore()) &&
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(unsigned)RegUseIndex < UseTID.getNumOperands() &&
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UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
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LDataLatency += SpecialAddressLatency;
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}
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UseSU->addPred(SDep(SU, SDep::Data, LDataLatency, Reg));
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}
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}
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU != SU)
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UseSU->addPred(SDep(SU, SDep::Data, DataLatency, *Alias));
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}
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}
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// If a def is going to wrap back around to the top of the loop,
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// backschedule it.
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// TODO: Blocks in loops without terminators can benefit too.
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if (!UnitLatencies && Terminator && DefList.empty()) {
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LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
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if (I != LoopRegs.Deps.end()) {
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const MachineOperand *UseMO = I->second.first;
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unsigned Count = I->second.second;
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const MachineInstr *UseMI = UseMO->getParent();
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unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
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const TargetInstrDesc &UseTID = UseMI->getDesc();
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// TODO: If we knew the total depth of the region here, we could
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// handle the case where the whole loop is inside the region but
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// is large enough that the isScheduleHigh trick isn't needed.
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if (UseMOIdx < UseTID.getNumOperands()) {
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// Currently, we only support scheduling regions consisting of
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// single basic blocks. Check to see if the instruction is in
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// the same region by checking to see if it has the same parent.
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if (UseMI->getParent() != MI->getParent()) {
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unsigned Latency = SU->Latency;
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if (UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass())
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Latency += SpecialAddressLatency;
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// This is a wild guess as to the portion of the latency which
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// will be overlapped by work done outside the current
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// scheduling region.
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Latency -= std::min(Latency, Count);
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// Add the artifical edge.
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Terminator->addPred(SDep(SU, SDep::Order, Latency,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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} else if (SpecialAddressLatency > 0 &&
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UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
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// The entire loop body is within the current scheduling region
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// and the latency of this operation is assumed to be greater
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// than the latency of the loop.
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// TODO: Recursively mark data-edge predecessors as
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// isScheduleHigh too.
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SU->isScheduleHigh = true;
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}
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}
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LoopRegs.Deps.erase(I);
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}
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}
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UseList.clear();
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if (!MO.isDead())
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DefList.clear();
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DefList.push_back(SU);
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} else {
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UseList.push_back(SU);
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}
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}
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// Add chain dependencies.
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// Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
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// after stack slots are lowered to actual addresses.
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// TODO: Use an AliasAnalysis and do real alias-analysis queries, and
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// produce more precise dependence information.
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if (TID.isCall() || TID.isTerminator() || TID.hasUnmodeledSideEffects()) {
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new_chain:
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// This is the conservative case. Add dependencies on all memory
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// references.
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if (Chain)
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Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
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Chain = SU;
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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PendingLoads[k]->addPred(SDep(SU, SDep::Order, SU->Latency));
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PendingLoads.clear();
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for (std::map<const Value *, SUnit *>::iterator I = MemDefs.begin(),
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E = MemDefs.end(); I != E; ++I) {
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I->second->addPred(SDep(SU, SDep::Order, SU->Latency));
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I->second = SU;
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}
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for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
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MemUses.begin(), E = MemUses.end(); I != E; ++I) {
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for (unsigned i = 0, e = I->second.size(); i != e; ++i)
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I->second[i]->addPred(SDep(SU, SDep::Order, SU->Latency));
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I->second.clear();
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}
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// See if it is known to just have a single memory reference.
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MachineInstr *ChainMI = Chain->getInstr();
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const TargetInstrDesc &ChainTID = ChainMI->getDesc();
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if (!ChainTID.isCall() && !ChainTID.isTerminator() &&
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!ChainTID.hasUnmodeledSideEffects() &&
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ChainMI->hasOneMemOperand() &&
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!ChainMI->memoperands_begin()->isVolatile() &&
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ChainMI->memoperands_begin()->getValue())
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// We know that the Chain accesses one specific memory location.
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ChainMMO = &*ChainMI->memoperands_begin();
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else
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// Unknown memory accesses. Assume the worst.
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ChainMMO = 0;
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} else if (TID.mayStore()) {
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if (MI->hasOneMemOperand() &&
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MI->memoperands_begin()->getValue() &&
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!MI->memoperands_begin()->isVolatile() &&
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isa<PseudoSourceValue>(MI->memoperands_begin()->getValue())) {
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// A store to a specific PseudoSourceValue. Add precise dependencies.
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const Value *V = MI->memoperands_begin()->getValue();
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// Handle the def in MemDefs, if there is one.
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std::map<const Value *, SUnit *>::iterator I = MemDefs.find(V);
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if (I != MemDefs.end()) {
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I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
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/*isNormalMemory=*/true));
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I->second = SU;
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} else {
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MemDefs[V] = SU;
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}
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// Handle the uses in MemUses, if there are any.
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std::map<const Value *, std::vector<SUnit *> >::iterator J =
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MemUses.find(V);
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if (J != MemUses.end()) {
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for (unsigned i = 0, e = J->second.size(); i != e; ++i)
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J->second[i]->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
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/*isNormalMemory=*/true));
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J->second.clear();
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}
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// Add a general dependence too, if needed.
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if (Chain)
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Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
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} else
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// Treat all other stores conservatively.
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goto new_chain;
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} else if (TID.mayLoad()) {
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if (TII->isInvariantLoad(MI)) {
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// Invariant load, no chain dependencies needed!
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} else if (MI->hasOneMemOperand() &&
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MI->memoperands_begin()->getValue() &&
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!MI->memoperands_begin()->isVolatile() &&
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isa<PseudoSourceValue>(MI->memoperands_begin()->getValue())) {
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// A load from a specific PseudoSourceValue. Add precise dependencies.
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const Value *V = MI->memoperands_begin()->getValue();
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std::map<const Value *, SUnit *>::iterator I = MemDefs.find(V);
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if (I != MemDefs.end())
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I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0,
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/*isNormalMemory=*/true));
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MemUses[V].push_back(SU);
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// Add a general dependence too, if needed.
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if (Chain && (!ChainMMO ||
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(ChainMMO->isStore() || ChainMMO->isVolatile())))
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Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
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} else if (MI->hasVolatileMemoryRef()) {
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// Treat volatile loads conservatively. Note that this includes
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// cases where memoperand information is unavailable.
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goto new_chain;
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} else {
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// A normal load. Just depend on the general chain.
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if (Chain)
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Chain->addPred(SDep(SU, SDep::Order, SU->Latency));
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PendingLoads.push_back(SU);
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}
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}
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// Add chain edges from the terminator to ensure that all the work of the
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// block is completed before any control transfers.
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if (Terminator && SU->Succs.empty())
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Terminator->addPred(SDep(SU, SDep::Order, SU->Latency));
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if (TID.isTerminator() || MI->isLabel())
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Terminator = SU;
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}
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for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
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Defs[i].clear();
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Uses[i].clear();
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}
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PendingLoads.clear();
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}
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void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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// Compute the latency for the node. We use the sum of the latencies for
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// all nodes flagged together into this SUnit.
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SU->Latency =
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InstrItins.getLatency(SU->getInstr()->getDesc().getSchedClass());
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// Simplistic target-independent heuristic: assume that loads take
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// extra time.
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if (InstrItins.isEmpty())
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if (SU->getInstr()->getDesc().mayLoad())
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SU->Latency += 2;
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}
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void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
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SU->getInstr()->dump();
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}
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std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
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std::string s;
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raw_string_ostream oss(s);
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SU->getInstr()->print(oss);
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return oss.str();
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}
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// EmitSchedule - Emit the machine code in scheduled order.
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MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
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// For MachineInstr-based scheduling, we're rescheduling the instructions in
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// the block, so start by removing them from the block.
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while (!BB->empty())
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BB->remove(BB->begin());
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// Then re-insert them according to the given schedule.
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for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
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SUnit *SU = Sequence[i];
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if (!SU) {
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// Null SUnit* is a noop.
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EmitNoop();
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continue;
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}
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BB->push_back(SU->getInstr());
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}
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return BB;
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}
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