Jim Grosbach e1cf5902ec ARM SRS instruction parsing, diassembly and encoding support. ... Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-29 20:26:09 +00:00
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ARM	ARM SRS instruction parsing, diassembly and encoding support.	2011-07-29 20:26:09 +00:00
MBlaze	Teach the MBlaze disassembler to disassemble special purpose registers.	2010-12-20 21:18:04 +00:00
X86	Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.	2011-07-16 02:41:28 +00:00