mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
1.5 KiB
LLVM
73 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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define i32 @f1(i32* %v) {
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entry:
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; CHECK: f1:
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; CHECK: ldr r0, [r0]
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%tmp = load i32* %v
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ret i32 %tmp
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}
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define i32 @f2(i32* %v) {
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entry:
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; CHECK: f2:
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; CHECK: ldr.w r0, [r0, #+4092]
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%tmp2 = getelementptr i32* %v, i32 1023
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%tmp = load i32* %tmp2
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ret i32 %tmp
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}
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define i32 @f3(i32* %v) {
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entry:
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; CHECK: f3:
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; CHECK: mov.w r1, #4096
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; CHECK: ldr r0, [r0, r1]
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%tmp2 = getelementptr i32* %v, i32 1024
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%tmp = load i32* %tmp2
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ret i32 %tmp
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}
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define i32 @f4(i32 %base) {
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entry:
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; CHECK: f4:
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; CHECK: ldr r0, [r0, #-128]
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%tmp1 = sub i32 %base, 128
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%tmp2 = inttoptr i32 %tmp1 to i32*
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%tmp3 = load i32* %tmp2
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ret i32 %tmp3
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}
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define i32 @f5(i32 %base, i32 %offset) {
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entry:
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; CHECK: f5:
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; CHECK: ldr r0, [r0, r1]
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%tmp1 = add i32 %base, %offset
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%tmp2 = inttoptr i32 %tmp1 to i32*
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%tmp3 = load i32* %tmp2
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ret i32 %tmp3
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}
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define i32 @f6(i32 %base, i32 %offset) {
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entry:
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; CHECK: f6:
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; CHECK: ldr.w r0, [r0, r1, lsl #2]
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i32*
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%tmp4 = load i32* %tmp3
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ret i32 %tmp4
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}
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define i32 @f7(i32 %base, i32 %offset) {
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entry:
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; CHECK: f7:
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; CHECK: lsrs r1, r1, #2
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; CHECK: ldr r0, [r0, r1]
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%tmp1 = lshr i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i32*
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%tmp4 = load i32* %tmp3
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ret i32 %tmp4
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}
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