mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-11 08:07:22 +00:00
c0b0c677a1
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
3.1 KiB
C++
79 lines
3.1 KiB
C++
//===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief R600 DAG Lowering interface definition
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef R600ISELLOWERING_H
|
|
#define R600ISELLOWERING_H
|
|
|
|
#include "AMDGPUISelLowering.h"
|
|
|
|
namespace llvm {
|
|
|
|
class R600InstrInfo;
|
|
|
|
class R600TargetLowering : public AMDGPUTargetLowering {
|
|
public:
|
|
R600TargetLowering(TargetMachine &TM);
|
|
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock * BB) const;
|
|
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
|
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
void ReplaceNodeResults(SDNode * N,
|
|
SmallVectorImpl<SDValue> &Results,
|
|
SelectionDAG &DAG) const;
|
|
virtual SDValue LowerFormalArguments(
|
|
SDValue Chain,
|
|
CallingConv::ID CallConv,
|
|
bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
DebugLoc DL, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
virtual EVT getSetCCResultType(EVT VT) const;
|
|
private:
|
|
const R600InstrInfo * TII;
|
|
|
|
/// Each OpenCL kernel has nine implicit parameters that are stored in the
|
|
/// first nine dwords of a Vertex Buffer. These implicit parameters are
|
|
/// lowered to load instructions which retreive the values from the Vertex
|
|
/// Buffer.
|
|
SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
|
|
DebugLoc DL, unsigned DwordOffset) const;
|
|
|
|
void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
|
|
MachineRegisterInfo & MRI, unsigned dword_offset) const;
|
|
|
|
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
/// \brief Lower ROTL opcode to BITALIGN
|
|
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFPOW(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
|
|
SelectionDAG &DAG) const;
|
|
void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
|
|
unsigned &Channel, unsigned &PtrIncr) const;
|
|
bool isZero(SDValue Op) const;
|
|
};
|
|
|
|
} // End namespace llvm;
|
|
|
|
#endif // R600ISELLOWERING_H
|