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49e163b6c749a6118939fbba19664b96c2089cfc
llvm-6502/lib/Target/ARM/Disassembler
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Owen Anderson 49e163b6c7 Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135319 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 22:49:31 +00:00
..
ARMDisassembler.cpp
Fix typo in the comment.
2011-04-19 23:58:52 +00:00
ARMDisassembler.h
Better error handling of invalid IT mask '0000', instead of just asserting.
2010-04-19 23:02:58 +00:00
ARMDisassemblerCore.cpp
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
2011-07-15 18:46:47 +00:00
ARMDisassemblerCore.h
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
2011-04-12 17:09:04 +00:00
CMakeLists.txt
CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86.
2010-12-29 03:59:27 +00:00
Makefile
…
ThumbDisassemblerCore.h
Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
2011-07-15 22:49:31 +00:00
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