mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0998627b24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155915 91177308-0d34-0410-b5e6-96231b3b80d8
557 lines
20 KiB
C++
557 lines
20 KiB
C++
//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Mips Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "llvm/MC/EDInstInfo.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/MathExtras.h"
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#include "MipsGenEDInfo.inc"
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// MipsDisassembler - a disasembler class for Mips32.
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class MipsDisassembler : public MCDisassembler {
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public:
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/// Constructor - Initializes the disassembler.
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///
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MipsDisassembler(const MCSubtargetInfo &STI, bool bigEndian) :
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MCDisassembler(STI), isBigEndian(bigEndian) {
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}
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~MipsDisassembler() {
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}
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/// getInstruction - See MCDisassembler.
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DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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/// getEDInfo - See MCDisassembler.
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const EDInstInfo *getEDInfo() const;
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private:
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bool isBigEndian;
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};
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/// Mips64Disassembler - a disasembler class for Mips64.
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class Mips64Disassembler : public MCDisassembler {
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public:
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/// Constructor - Initializes the disassembler.
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///
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Mips64Disassembler(const MCSubtargetInfo &STI, bool bigEndian) :
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MCDisassembler(STI), isBigEndian(bigEndian) {
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}
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~Mips64Disassembler() {
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}
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/// getInstruction - See MCDisassembler.
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DecodeStatus getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const;
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/// getEDInfo - See MCDisassembler.
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const EDInstInfo *getEDInfo() const;
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private:
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bool isBigEndian;
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};
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} // end anonymous namespace
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const EDInstInfo *MipsDisassembler::getEDInfo() const {
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return instInfoMips;
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}
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const EDInstInfo *Mips64Disassembler::getEDInfo() const {
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return instInfoMips;
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}
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// Decoder tables for Mips register
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static const unsigned CPURegsTable[] = {
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Mips::ZERO, Mips::AT, Mips::V0, Mips::V1,
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Mips::A0, Mips::A1, Mips::A2, Mips::A3,
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Mips::T0, Mips::T1, Mips::T2, Mips::T3,
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Mips::T4, Mips::T5, Mips::T6, Mips::T7,
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Mips::S0, Mips::S1, Mips::S2, Mips::S3,
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Mips::S4, Mips::S5, Mips::S6, Mips::S7,
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Mips::T8, Mips::T9, Mips::K0, Mips::K1,
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Mips::GP, Mips::SP, Mips::FP, Mips::RA
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};
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static const unsigned FGR32RegsTable[] = {
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Mips::F0, Mips::F1, Mips::F2, Mips::F3,
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Mips::F4, Mips::F5, Mips::F6, Mips::F7,
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Mips::F8, Mips::F9, Mips::F10, Mips::F11,
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Mips::F12, Mips::F13, Mips::F14, Mips::F15,
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Mips::F16, Mips::F17, Mips::F18, Mips::F18,
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Mips::F20, Mips::F21, Mips::F22, Mips::F23,
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Mips::F24, Mips::F25, Mips::F26, Mips::F27,
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Mips::F28, Mips::F29, Mips::F30, Mips::F31
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};
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static const unsigned CPU64RegsTable[] = {
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Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64,
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
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Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64,
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Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64,
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Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64,
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Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64,
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Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64,
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Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
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};
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static const unsigned FGR64RegsTable[] = {
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Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64,
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Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64,
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Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64,
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Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
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Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64,
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Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64,
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Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64,
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Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64
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};
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static const unsigned AFGR64RegsTable[] = {
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Mips::D0, Mips::D1, Mips::D2, Mips::D3,
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Mips::D4, Mips::D5, Mips::D6, Mips::D7,
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Mips::D8, Mips::D9, Mips::D10, Mips::D11,
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Mips::D12, Mips::D13, Mips::D14, Mips::D15
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};
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// Forward declare these because the autogenerated code will reference them.
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// Definitions are further down.
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static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBC1(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSimm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeCondCode(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeInsSize(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeExtSize(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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namespace llvm {
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extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
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TheMips64elTarget;
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}
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static MCDisassembler *createMipsDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new MipsDisassembler(STI,true);
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}
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static MCDisassembler *createMipselDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new MipsDisassembler(STI,false);
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}
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static MCDisassembler *createMips64Disassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new Mips64Disassembler(STI,true);
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}
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static MCDisassembler *createMips64elDisassembler(
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const Target &T,
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const MCSubtargetInfo &STI) {
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return new Mips64Disassembler(STI, false);
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}
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extern "C" void LLVMInitializeMipsDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
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createMipsDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
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createMipselDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheMips64Target,
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createMips64Disassembler);
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TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
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createMips64elDisassembler);
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}
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#include "MipsGenDisassemblerTables.inc"
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/// readInstruction - read four bytes from the MemoryObject
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/// and return 32 bit word sorted according to the given endianess
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static DecodeStatus readInstruction32(const MemoryObject ®ion,
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uint64_t address,
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uint64_t &size,
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uint32_t &insn,
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bool isBigEndian) {
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uint8_t Bytes[4];
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// We want to read exactly 4 Bytes of data.
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if (region.readBytes(address, 4, (uint8_t*)Bytes, NULL) == -1) {
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size = 0;
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return MCDisassembler::Fail;
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}
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if (isBigEndian) {
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// Encoded as a big-endian 32-bit word in the stream.
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insn = (Bytes[3] << 0) |
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(Bytes[2] << 8) |
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(Bytes[1] << 16) |
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(Bytes[0] << 24);
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}
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else {
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// Encoded as a small-endian 32-bit word in the stream.
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insn = (Bytes[0] << 0) |
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(Bytes[1] << 8) |
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(Bytes[2] << 16) |
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(Bytes[3] << 24);
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}
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return MCDisassembler::Success;
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}
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DecodeStatus
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MipsDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size,
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Insn, isBigEndian);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result = decodeMipsInstruction32(instr, Insn, Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus
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Mips64Disassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &vStream,
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raw_ostream &cStream) const {
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Region, Address, Size,
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Insn, isBigEndian);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result = decodeMips64Instruction32(instr, Insn, Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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// If we fail to decode in Mips64 decoder space we can try in Mips32
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Result = decodeMipsInstruction32(instr, Insn, Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(CPU64RegsTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(CPURegsTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(FGR32RegsTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
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int Base = (int)fieldFromInstruction32(Insn, 21, 5);
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if(Inst.getOpcode() == Mips::SC){
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Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
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}
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Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
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Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFMem(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Offset = SignExtend32<16>(Insn & 0xffff);
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int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
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int Base = (int)fieldFromInstruction32(Insn, 21, 5);
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Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[Reg]));
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Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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// Currently only hardware register 29 is supported.
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if (RegNo != 29)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCondCode(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int CondCode = Insn & 0xf;
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Inst.addOperand(MCOperand::CreateImm(CondCode));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(AFGR64RegsTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
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|
unsigned RegNo,
|
|
uint64_t Address,
|
|
const void *Decoder) {
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|
//Currently only hardware register 29 is supported
|
|
if (RegNo != 29)
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|
return MCDisassembler::Fail;
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|
Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
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|
return MCDisassembler::Success;
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|
}
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|
|
|
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
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|
unsigned Offset,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned BranchOffset = Offset & 0xffff;
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|
BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
|
|
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBC1(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
unsigned BranchOffset = Insn & 0xffff;
|
|
BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
|
|
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
|
|
unsigned JumpOffset = fieldFromInstruction32(Insn, 0, 26) << 2;
|
|
Inst.addOperand(MCOperand::CreateImm(JumpOffset));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
|
|
static DecodeStatus DecodeSimm16(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeInsSize(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
// First we need to grab the pos(lsb) from MCInst.
|
|
int Pos = Inst.getOperand(2).getImm();
|
|
int Size = (int) Insn - Pos + 1;
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeExtSize(MCInst &Inst,
|
|
unsigned Insn,
|
|
uint64_t Address,
|
|
const void *Decoder) {
|
|
int Size = (int) Insn + 1;
|
|
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
|
|
return MCDisassembler::Success;
|
|
}
|