mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-24 06:30:19 +00:00
49f846805e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76991 91177308-0d34-0410-b5e6-96231b3b80d8
1316 lines
44 KiB
C++
1316 lines
44 KiB
C++
//===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format ARM assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "ARM.h"
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#include "ARMBuildAttrs.h"
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#include "ARMTargetMachine.h"
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#include "ARMAddressingModes.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Module.h"
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#include "llvm/MDNode.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/DwarfWriter.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Mangler.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/FormattedStream.h"
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#include <cctype>
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using namespace llvm;
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STATISTIC(EmittedInsts, "Number of machine instrs printed");
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namespace {
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class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
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DwarfWriter *DW;
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when printing asm code for different targets.
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const ARMSubtarget *Subtarget;
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/// AFI - Keep a pointer to ARMFunctionInfo for the current
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/// MachineFunction.
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ARMFunctionInfo *AFI;
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/// MCP - Keep a pointer to constantpool entries of the current
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/// MachineFunction.
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const MachineConstantPool *MCP;
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/// We name each basic block in a Function with a unique number, so
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/// that we can consistently refer to them later. This is cleared
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/// at the beginning of each call to runOnMachineFunction().
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///
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typedef std::map<const Value *, unsigned> ValueMapTy;
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ValueMapTy NumberForBB;
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/// GVNonLazyPtrs - Keeps the set of GlobalValues that require
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/// non-lazy-pointers for indirect access.
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StringMap<std::string> GVNonLazyPtrs;
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/// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
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/// visibility that require non-lazy-pointers for indirect access.
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StringMap<std::string> HiddenGVNonLazyPtrs;
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struct FnStubInfo {
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std::string Stub, LazyPtr, SLP, SCV;
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FnStubInfo() {}
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void Init(const GlobalValue *GV, Mangler *Mang) {
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// Already initialized.
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if (!Stub.empty()) return;
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Stub = Mang->getMangledName(GV, "$stub", true);
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LazyPtr = Mang->getMangledName(GV, "$lazy_ptr", true);
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SLP = Mang->getMangledName(GV, "$slp", true);
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SCV = Mang->getMangledName(GV, "$scv", true);
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}
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void Init(const std::string &GV, Mangler *Mang) {
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// Already initialized.
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if (!Stub.empty()) return;
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Stub = Mang->makeNameProper(GV + "$stub", Mangler::Private);
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LazyPtr = Mang->makeNameProper(GV + "$lazy_ptr", Mangler::Private);
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SLP = Mang->makeNameProper(GV + "$slp", Mangler::Private);
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SCV = Mang->makeNameProper(GV + "$scv", Mangler::Private);
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}
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};
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/// FnStubs - Keeps the set of external function GlobalAddresses that the
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/// asm printer should generate stubs for.
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StringMap<FnStubInfo> FnStubs;
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/// True if asm printer is printing a series of CONSTPOOL_ENTRY.
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bool InCPMode;
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public:
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explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
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const TargetAsmInfo *T, bool V)
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: AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
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InCPMode(false) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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}
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virtual const char *getPassName() const {
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return "ARM Assembly Printer";
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}
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void printOperand(const MachineInstr *MI, int OpNum,
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const char *Modifier = 0);
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void printSOImmOperand(const MachineInstr *MI, int OpNum);
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void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
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void printSORegOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
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void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
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void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
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void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
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const char *Modifier = 0);
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void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
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const char *Modifier = 0);
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void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
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void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
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const char *Modifier = 0);
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void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
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void printThumbITMask(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
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unsigned Scale);
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void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
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void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
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void printT2SOOperand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
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void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
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void printPredicateOperand(const MachineInstr *MI, int OpNum);
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void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
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void printPCLabel(const MachineInstr *MI, int OpNum);
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void printRegisterList(const MachineInstr *MI, int OpNum);
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void printCPInstOperand(const MachineInstr *MI, int OpNum,
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const char *Modifier);
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void printJTBlockOperand(const MachineInstr *MI, int OpNum);
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virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode);
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virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant,
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const char *ExtraCode);
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void PrintGlobalVariable(const GlobalVariable* GVar);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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void printMachineInstruction(const MachineInstr *MI);
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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bool doFinalization(Module &M);
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/// EmitMachineConstantPoolValue - Print a machine constantpool value to
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/// the .s file.
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virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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printDataDirective(MCPV->getType());
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ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
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GlobalValue *GV = ACPV->getGV();
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std::string Name;
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if (ACPV->isNonLazyPointer()) {
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std::string SymName = Mang->getMangledName(GV);
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Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
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if (GV->hasHiddenVisibility())
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HiddenGVNonLazyPtrs[SymName] = Name;
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else
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GVNonLazyPtrs[SymName] = Name;
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} else if (ACPV->isStub()) {
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if (GV) {
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FnStubInfo &FnInfo = FnStubs[Mang->getMangledName(GV)];
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FnInfo.Init(GV, Mang);
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Name = FnInfo.Stub;
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} else {
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FnStubInfo &FnInfo = FnStubs[Mang->makeNameProper(ACPV->getSymbol())];
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FnInfo.Init(ACPV->getSymbol(), Mang);
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Name = FnInfo.Stub;
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}
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} else {
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if (GV)
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Name = Mang->getMangledName(GV);
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else
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Name = Mang->makeNameProper(ACPV->getSymbol());
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}
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O << Name;
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if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
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if (ACPV->getPCAdjustment() != 0) {
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O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
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<< utostr(ACPV->getLabelId())
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<< "+" << (unsigned)ACPV->getPCAdjustment();
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if (ACPV->mustAddCurrentAddress())
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O << "-.";
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O << ")";
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}
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O << "\n";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AsmPrinter::getAnalysisUsage(AU);
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AU.setPreservesAll();
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AU.addRequired<MachineModuleInfo>();
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AU.addRequired<DwarfWriter>();
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}
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};
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} // end of anonymous namespace
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#include "ARMGenAsmWriter.inc"
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/// runOnMachineFunction - This uses the printInstruction()
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/// method to print assembly for each instruction.
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///
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bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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this->MF = &MF;
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AFI = MF.getInfo<ARMFunctionInfo>();
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MCP = MF.getConstantPool();
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SetupMachineFunction(MF);
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O << "\n";
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// NOTE: we don't print out constant pools here, they are handled as
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// instructions.
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O << "\n";
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// Print out labels for the function.
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const Function *F = MF.getFunction();
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switch (F->getLinkage()) {
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default: llvm_unreachable("Unknown linkage type!");
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case Function::PrivateLinkage:
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case Function::LinkerPrivateLinkage:
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case Function::InternalLinkage:
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SwitchToTextSection("\t.text", F);
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break;
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case Function::ExternalLinkage:
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SwitchToTextSection("\t.text", F);
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O << "\t.globl\t" << CurrentFnName << "\n";
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break;
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case Function::WeakAnyLinkage:
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case Function::WeakODRLinkage:
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case Function::LinkOnceAnyLinkage:
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case Function::LinkOnceODRLinkage:
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if (Subtarget->isTargetDarwin()) {
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SwitchToTextSection(
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".section __TEXT,__textcoal_nt,coalesced,pure_instructions", F);
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O << "\t.globl\t" << CurrentFnName << "\n";
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O << "\t.weak_definition\t" << CurrentFnName << "\n";
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} else {
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O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
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}
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break;
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}
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printVisibility(CurrentFnName, F->getVisibility());
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if (AFI->isThumbFunction()) {
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EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
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O << "\t.code\t16\n";
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O << "\t.thumb_func";
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if (Subtarget->isTargetDarwin())
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O << "\t" << CurrentFnName;
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O << "\n";
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InCPMode = false;
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} else {
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EmitAlignment(MF.getAlignment(), F);
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}
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O << CurrentFnName << ":\n";
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// Emit pre-function debug information.
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DW->BeginFunction(&MF);
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if (Subtarget->isTargetDarwin()) {
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// If the function is empty, then we need to emit *something*. Otherwise,
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// the function's label might be associated with something that it wasn't
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// meant to be associated with. We emit a noop in this situation.
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MachineFunction::iterator I = MF.begin();
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if (++I == MF.end() && MF.front().empty())
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O << "\tnop\n";
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}
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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if (I != MF.begin()) {
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printBasicBlockLabel(I, true, true, VerboseAsm);
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O << '\n';
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}
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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printMachineInstruction(II);
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}
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}
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if (TAI->hasDotTypeDotSizeDirective())
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O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
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// Emit post-function debug information.
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DW->EndFunction(&MF);
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O.flush();
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return false;
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}
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void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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const char *Modifier) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (MO.getType()) {
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case MachineOperand::MO_Register: {
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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if (Modifier && strcmp(Modifier, "dregpair") == 0) {
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unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
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unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
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O << '{'
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<< TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
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<< '}';
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} else if (Modifier && strcmp(Modifier, "dregsingle") == 0) {
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O << '{' << TRI->getAsmName(Reg) << '}';
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} else {
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O << TRI->getAsmName(Reg);
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}
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} else
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llvm_unreachable("not implemented");
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break;
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}
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case MachineOperand::MO_Immediate: {
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if (!Modifier || strcmp(Modifier, "no_hash") != 0)
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O << "#";
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O << MO.getImm();
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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printBasicBlockLabel(MO.getMBB());
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return;
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case MachineOperand::MO_GlobalAddress: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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GlobalValue *GV = MO.getGlobal();
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std::string Name;
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bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
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if (isExt && isCallOp && Subtarget->isTargetDarwin() &&
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TM.getRelocationModel() != Reloc::Static) {
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FnStubInfo &FnInfo = FnStubs[Mang->getMangledName(GV)];
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FnInfo.Init(GV, Mang);
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Name = FnInfo.Stub;
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} else {
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Name = Mang->getMangledName(GV);
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}
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O << Name;
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printOffset(MO.getOffset());
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if (isCallOp && Subtarget->isTargetELF() &&
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TM.getRelocationModel() == Reloc::PIC_)
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O << "(PLT)";
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break;
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}
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case MachineOperand::MO_ExternalSymbol: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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std::string Name;
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if (isCallOp && Subtarget->isTargetDarwin() &&
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TM.getRelocationModel() != Reloc::Static) {
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FnStubInfo &FnInfo = FnStubs[Mang->makeNameProper(MO.getSymbolName())];
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FnInfo.Init(MO.getSymbolName(), Mang);
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Name = FnInfo.Stub;
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} else
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Name = Mang->makeNameProper(MO.getSymbolName());
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O << Name;
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if (isCallOp && Subtarget->isTargetELF() &&
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TM.getRelocationModel() == Reloc::PIC_)
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O << "(PLT)";
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break;
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}
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case MachineOperand::MO_ConstantPoolIndex:
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O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
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<< '_' << MO.getIndex();
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break;
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case MachineOperand::MO_JumpTableIndex:
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O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
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<< '_' << MO.getIndex();
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break;
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default:
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O << "<unknown operand type>"; abort (); break;
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}
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}
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static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
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const TargetAsmInfo *TAI) {
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// Break it up into two parts that make up a shifter immediate.
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V = ARM_AM::getSOImmVal(V);
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assert(V != -1 && "Not a valid so_imm value!");
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unsigned Imm = ARM_AM::getSOImmValImm(V);
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unsigned Rot = ARM_AM::getSOImmValRot(V);
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// Print low-level immediate formation info, per
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// A5.1.3: "Data-processing operands - Immediate".
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if (Rot) {
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O << "#" << Imm << ", " << Rot;
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// Pretty printed version.
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if (VerboseAsm)
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O << ' ' << TAI->getCommentString()
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<< ' ' << (int)ARM_AM::rotr32(Imm, Rot);
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} else {
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O << "#" << Imm;
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}
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}
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/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
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/// immediate in bits 0-7.
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void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isImm() && "Not a valid so_imm value!");
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printSOImm(O, MO.getImm(), VerboseAsm, TAI);
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}
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/// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
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/// followed by an 'orr' to materialize.
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void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isImm() && "Not a valid so_imm value!");
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unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
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unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
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printSOImm(O, V1, VerboseAsm, TAI);
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O << "\n\torr";
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printPredicateOperand(MI, 2);
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|
O << " ";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printSOImm(O, V2, VerboseAsm, TAI);
|
|
}
|
|
|
|
// so_reg is a 4-operand unit corresponding to register forms of the A5.1
|
|
// "Addressing Mode 1 - Data-processing operands" forms. This includes:
|
|
// REG 0 0 - e.g. R5
|
|
// REG REG 0,SH_OPC - e.g. R5, ROR R3
|
|
// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
|
|
void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
|
O << TRI->getAsmName(MO1.getReg());
|
|
|
|
// Print the shift opc.
|
|
O << ", "
|
|
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
|
|
<< " ";
|
|
|
|
if (MO2.getReg()) {
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
|
|
O << TRI->getAsmName(MO2.getReg());
|
|
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
|
|
} else {
|
|
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
|
|
}
|
|
}
|
|
|
|
void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, Op);
|
|
return;
|
|
}
|
|
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
|
|
if (!MO2.getReg()) {
|
|
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
|
|
O << ", #"
|
|
<< (char)ARM_AM::getAM2Op(MO3.getImm())
|
|
<< ARM_AM::getAM2Offset(MO3.getImm());
|
|
O << "]";
|
|
return;
|
|
}
|
|
|
|
O << ", "
|
|
<< (char)ARM_AM::getAM2Op(MO3.getImm())
|
|
<< TRI->getAsmName(MO2.getReg());
|
|
|
|
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
|
|
O << ", "
|
|
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
|
|
<< " #" << ShImm;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
if (!MO1.getReg()) {
|
|
unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
|
|
assert(ImmOffs && "Malformed indexed load / store!");
|
|
O << "#"
|
|
<< (char)ARM_AM::getAM2Op(MO2.getImm())
|
|
<< ImmOffs;
|
|
return;
|
|
}
|
|
|
|
O << (char)ARM_AM::getAM2Op(MO2.getImm())
|
|
<< TRI->getAsmName(MO1.getReg());
|
|
|
|
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
|
|
O << ", "
|
|
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
|
|
<< " #" << ShImm;
|
|
}
|
|
|
|
void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
|
|
if (MO2.getReg()) {
|
|
O << ", "
|
|
<< (char)ARM_AM::getAM3Op(MO3.getImm())
|
|
<< TRI->getAsmName(MO2.getReg())
|
|
<< "]";
|
|
return;
|
|
}
|
|
|
|
if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
|
|
O << ", #"
|
|
<< (char)ARM_AM::getAM3Op(MO3.getImm())
|
|
<< ImmOffs;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
if (MO1.getReg()) {
|
|
O << (char)ARM_AM::getAM3Op(MO2.getImm())
|
|
<< TRI->getAsmName(MO1.getReg());
|
|
return;
|
|
}
|
|
|
|
unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
|
|
assert(ImmOffs && "Malformed indexed load / store!");
|
|
O << "#"
|
|
<< (char)ARM_AM::getAM3Op(MO2.getImm())
|
|
<< ImmOffs;
|
|
}
|
|
|
|
void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
|
|
const char *Modifier) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
|
|
if (Modifier && strcmp(Modifier, "submode") == 0) {
|
|
if (MO1.getReg() == ARM::SP) {
|
|
bool isLDM = (MI->getOpcode() == ARM::LDM ||
|
|
MI->getOpcode() == ARM::LDM_RET);
|
|
O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
|
|
} else
|
|
O << ARM_AM::getAMSubModeStr(Mode);
|
|
} else {
|
|
printOperand(MI, Op);
|
|
if (ARM_AM::getAM4WBFlag(MO2.getImm()))
|
|
O << "!";
|
|
}
|
|
}
|
|
|
|
void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
|
|
const char *Modifier) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, Op);
|
|
return;
|
|
}
|
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
|
|
|
if (Modifier && strcmp(Modifier, "submode") == 0) {
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
|
|
if (MO1.getReg() == ARM::SP) {
|
|
bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
|
|
MI->getOpcode() == ARM::FLDMS);
|
|
O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
|
|
} else
|
|
O << ARM_AM::getAMSubModeStr(Mode);
|
|
return;
|
|
} else if (Modifier && strcmp(Modifier, "base") == 0) {
|
|
// Used for FSTM{D|S} and LSTM{D|S} operations.
|
|
O << TRI->getAsmName(MO1.getReg());
|
|
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
|
|
O << "!";
|
|
return;
|
|
}
|
|
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
|
|
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
|
|
O << ", #"
|
|
<< (char)ARM_AM::getAM5Op(MO2.getImm())
|
|
<< ImmOffs*4;
|
|
}
|
|
O << "]";
|
|
}
|
|
|
|
void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
// FIXME: No support yet for specifying alignment.
|
|
O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
|
|
|
|
if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
|
|
if (MO2.getReg() == 0)
|
|
O << "!";
|
|
else
|
|
O << ", " << TRI->getAsmName(MO2.getReg());
|
|
}
|
|
}
|
|
|
|
void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
|
|
const char *Modifier) {
|
|
if (Modifier && strcmp(Modifier, "label") == 0) {
|
|
printPCLabel(MI, Op+1);
|
|
return;
|
|
}
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
|
O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
|
|
}
|
|
|
|
void
|
|
ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
|
|
const MachineOperand &MO = MI->getOperand(Op);
|
|
uint32_t v = ~MO.getImm();
|
|
int32_t lsb = CountTrailingZeros_32(v);
|
|
int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
|
|
assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
|
|
O << "#" << lsb << ", #" << width;
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
void
|
|
ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
|
|
// (3 - the number of trailing zeros) is the number of then / else.
|
|
unsigned Mask = MI->getOperand(Op).getImm();
|
|
unsigned NumTZ = CountTrailingZeros_32(Mask);
|
|
assert(NumTZ <= 3 && "Invalid IT mask!");
|
|
for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
|
|
bool T = (Mask & (1 << Pos)) != 0;
|
|
if (T)
|
|
O << 't';
|
|
else
|
|
O << 'e';
|
|
}
|
|
}
|
|
|
|
void
|
|
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
|
|
}
|
|
|
|
void
|
|
ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
|
|
unsigned Scale) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, Op);
|
|
return;
|
|
}
|
|
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
if (MO3.getReg())
|
|
O << ", " << TRI->getAsmName(MO3.getReg());
|
|
else if (unsigned ImmOffs = MO2.getImm()) {
|
|
O << ", #" << ImmOffs;
|
|
if (Scale > 1)
|
|
O << " * " << Scale;
|
|
}
|
|
O << "]";
|
|
}
|
|
|
|
void
|
|
ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
|
|
printThumbAddrModeRI5Operand(MI, Op, 1);
|
|
}
|
|
void
|
|
ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
|
|
printThumbAddrModeRI5Operand(MI, Op, 2);
|
|
}
|
|
void
|
|
ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
|
|
printThumbAddrModeRI5Operand(MI, Op, 4);
|
|
}
|
|
|
|
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
|
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
if (unsigned ImmOffs = MO2.getImm())
|
|
O << ", #" << ImmOffs << " * 4";
|
|
O << "]";
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
|
|
// register with shift forms.
|
|
// REG 0 0 - e.g. R5
|
|
// REG IMM, SH_OPC - e.g. R5, LSL #3
|
|
void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
unsigned Reg = MO1.getReg();
|
|
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
|
|
O << TRI->getAsmName(Reg);
|
|
|
|
// Print the shift opc.
|
|
O << ", "
|
|
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
|
|
<< " ";
|
|
|
|
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
|
|
O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
|
|
}
|
|
|
|
void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
|
|
int OpNum) {
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
|
|
unsigned OffImm = MO2.getImm();
|
|
if (OffImm) // Don't print +0.
|
|
O << ", #+" << OffImm;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
|
|
int OpNum) {
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << ", #-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << ", #+" << OffImm;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
|
|
int OpNum) {
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm() / 4;
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << ", #-" << -OffImm << " * 4";
|
|
else if (OffImm > 0)
|
|
O << ", #+" << OffImm << " * 4";
|
|
O << "]";
|
|
}
|
|
|
|
void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
|
|
int OpNum) {
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
int32_t OffImm = (int32_t)MO1.getImm();
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << "#-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << "#+" << OffImm;
|
|
}
|
|
|
|
void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
|
|
int OpNum) {
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
|
|
const MachineOperand &MO3 = MI->getOperand(OpNum+2);
|
|
|
|
O << "[" << TRI->getAsmName(MO1.getReg());
|
|
|
|
if (MO2.getReg()) {
|
|
O << ", +" << TRI->getAsmName(MO2.getReg());
|
|
|
|
unsigned ShAmt = MO3.getImm();
|
|
if (ShAmt) {
|
|
assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
|
|
O << ", lsl #" << ShAmt;
|
|
}
|
|
}
|
|
O << "]";
|
|
}
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
|
|
if (CC != ARMCC::AL)
|
|
O << ARMCondCodeToString(CC);
|
|
}
|
|
|
|
void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
|
if (Reg) {
|
|
assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
|
|
O << 's';
|
|
}
|
|
}
|
|
|
|
void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
|
|
int Id = (int)MI->getOperand(OpNum).getImm();
|
|
O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
|
|
}
|
|
|
|
void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
|
|
O << "{";
|
|
for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
|
|
printOperand(MI, i);
|
|
if (i != e-1) O << ", ";
|
|
}
|
|
O << "}";
|
|
}
|
|
|
|
void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
|
|
const char *Modifier) {
|
|
assert(Modifier && "This operand only works with a modifier!");
|
|
// There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
|
|
// data itself.
|
|
if (!strcmp(Modifier, "label")) {
|
|
unsigned ID = MI->getOperand(OpNum).getImm();
|
|
O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
|
|
<< '_' << ID << ":\n";
|
|
} else {
|
|
assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
|
|
unsigned CPI = MI->getOperand(OpNum).getIndex();
|
|
|
|
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
|
|
|
|
if (MCPE.isMachineConstantPoolEntry()) {
|
|
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
|
|
} else {
|
|
EmitGlobalConstant(MCPE.Val.ConstVal);
|
|
}
|
|
}
|
|
}
|
|
|
|
void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
|
unsigned JTI = MO1.getIndex();
|
|
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
|
|
<< '_' << JTI << '_' << MO2.getImm() << ":\n";
|
|
|
|
const char *JTEntryDirective = TAI->getJumpTableDirective();
|
|
if (!JTEntryDirective)
|
|
JTEntryDirective = TAI->getData32bitsDirective();
|
|
|
|
const MachineFunction *MF = MI->getParent()->getParent();
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
|
bool UseSet= TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
|
|
bool NeedBit0 = Subtarget->isTargetDarwin() && Subtarget->isThumb2();
|
|
SmallPtrSet<MachineBasicBlock*, 8> JTSets;
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
|
if (UseSet && JTSets.insert(MBB)) {
|
|
// FIXME: Temporary workaround for an assembler bug. The assembler isn't
|
|
// setting the bit zero to 1 even though it is a thumb address.
|
|
if (NeedBit0) {
|
|
O << TAI->getSetDirective() << ' ' << TAI->getPrivateGlobalPrefix()
|
|
<< getFunctionNumber() << '_' << JTI << '_' << MO2.getImm()
|
|
<< "_set_" << MBB->getNumber() << ",(";
|
|
printBasicBlockLabel(MBB, false, false, false);
|
|
O << '-' << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
|
|
<< '_' << JTI << '_' << MO2.getImm() << "+1)\n";
|
|
} else
|
|
printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
|
|
}
|
|
|
|
O << JTEntryDirective << ' ';
|
|
if (UseSet)
|
|
O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
|
|
<< '_' << JTI << '_' << MO2.getImm()
|
|
<< "_set_" << MBB->getNumber();
|
|
else if (TM.getRelocationModel() == Reloc::PIC_) {
|
|
printBasicBlockLabel(MBB, false, false, false);
|
|
// If the arch uses custom Jump Table directives, don't calc relative to JT
|
|
if (!TAI->getJumpTableDirective())
|
|
O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
|
|
<< getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
|
|
} else {
|
|
// FIXME: Temporary workaround for an assembler bug. The assembler isn't
|
|
// setting the bit zero to 1 even though it is a thumb address.
|
|
if (NeedBit0)
|
|
O << '(';
|
|
printBasicBlockLabel(MBB, false, false, false);
|
|
if (NeedBit0)
|
|
O << "+1)";
|
|
}
|
|
if (i != e-1)
|
|
O << '\n';
|
|
}
|
|
}
|
|
|
|
|
|
bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
|
unsigned AsmVariant, const char *ExtraCode){
|
|
// Does this asm operand have a single letter operand modifier?
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
|
|
|
switch (ExtraCode[0]) {
|
|
default: return true; // Unknown modifier.
|
|
case 'a': // Print as a memory address.
|
|
if (MI->getOperand(OpNum).isReg()) {
|
|
O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
|
|
return false;
|
|
}
|
|
// Fallthrough
|
|
case 'c': // Don't print "#" before an immediate operand.
|
|
printOperand(MI, OpNum, "no_hash");
|
|
return false;
|
|
case 'P': // Print a VFP double precision register.
|
|
printOperand(MI, OpNum);
|
|
return false;
|
|
case 'Q':
|
|
if (TM.getTargetData()->isLittleEndian())
|
|
break;
|
|
// Fallthrough
|
|
case 'R':
|
|
if (TM.getTargetData()->isBigEndian())
|
|
break;
|
|
// Fallthrough
|
|
case 'H': // Write second word of DI / DF reference.
|
|
// Verify that this operand has two consecutive registers.
|
|
if (!MI->getOperand(OpNum).isReg() ||
|
|
OpNum+1 == MI->getNumOperands() ||
|
|
!MI->getOperand(OpNum+1).isReg())
|
|
return true;
|
|
++OpNum; // Return the high-part.
|
|
}
|
|
}
|
|
|
|
printOperand(MI, OpNum);
|
|
return false;
|
|
}
|
|
|
|
bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
|
unsigned OpNum, unsigned AsmVariant,
|
|
const char *ExtraCode) {
|
|
if (ExtraCode && ExtraCode[0])
|
|
return true; // Unknown modifier.
|
|
printAddrMode2Operand(MI, OpNum);
|
|
return false;
|
|
}
|
|
|
|
void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
|
|
++EmittedInsts;
|
|
|
|
int Opc = MI->getOpcode();
|
|
switch (Opc) {
|
|
case ARM::CONSTPOOL_ENTRY:
|
|
if (!InCPMode && AFI->isThumbFunction()) {
|
|
EmitAlignment(2);
|
|
InCPMode = true;
|
|
}
|
|
break;
|
|
default: {
|
|
if (InCPMode && AFI->isThumbFunction())
|
|
InCPMode = false;
|
|
}}
|
|
|
|
// Call the autogenerated instruction printer routines.
|
|
printInstruction(MI);
|
|
}
|
|
|
|
bool ARMAsmPrinter::doInitialization(Module &M) {
|
|
|
|
bool Result = AsmPrinter::doInitialization(M);
|
|
DW = getAnalysisIfAvailable<DwarfWriter>();
|
|
|
|
// Use unified assembler syntax mode for Thumb.
|
|
if (Subtarget->isThumb())
|
|
O << "\t.syntax unified\n";
|
|
|
|
// Emit ARM Build Attributes
|
|
if (Subtarget->isTargetELF()) {
|
|
// CPU Type
|
|
std::string CPUString = Subtarget->getCPUString();
|
|
if (CPUString != "generic")
|
|
O << "\t.cpu " << CPUString << '\n';
|
|
|
|
// FIXME: Emit FPU type
|
|
if (Subtarget->hasVFP2())
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
|
|
|
|
// Signal various FP modes.
|
|
if (!UnsafeFPMath)
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
|
|
<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
|
|
|
|
if (FiniteOnlyFPMath())
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
|
|
else
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
|
|
|
|
// 8-bytes alignment stuff.
|
|
O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
|
|
<< "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
|
|
|
|
// FIXME: Should we signal R9 usage?
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
/// PrintUnmangledNameSafely - Print out the printable characters in the name.
|
|
/// Don't print things like \\n or \\0.
|
|
static void PrintUnmangledNameSafely(const Value *V, formatted_raw_ostream &OS) {
|
|
for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen();
|
|
Name != E; ++Name)
|
|
if (isprint(*Name))
|
|
OS << *Name;
|
|
}
|
|
|
|
void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
|
|
const TargetData *TD = TM.getTargetData();
|
|
|
|
if (!GVar->hasInitializer()) // External global require no code
|
|
return;
|
|
|
|
// Check to see if this is a special global used by LLVM, if so, emit it.
|
|
|
|
if (EmitSpecialLLVMGlobal(GVar)) {
|
|
if (Subtarget->isTargetDarwin() &&
|
|
TM.getRelocationModel() == Reloc::Static) {
|
|
if (GVar->isName("llvm.global_ctors"))
|
|
O << ".reference .constructors_used\n";
|
|
else if (GVar->isName("llvm.global_dtors"))
|
|
O << ".reference .destructors_used\n";
|
|
}
|
|
return;
|
|
}
|
|
|
|
std::string name = Mang->getMangledName(GVar);
|
|
Constant *C = GVar->getInitializer();
|
|
if (isa<MDNode>(C) || isa<MDString>(C))
|
|
return;
|
|
const Type *Type = C->getType();
|
|
unsigned Size = TD->getTypeAllocSize(Type);
|
|
unsigned Align = TD->getPreferredAlignmentLog(GVar);
|
|
bool isDarwin = Subtarget->isTargetDarwin();
|
|
|
|
printVisibility(name, GVar->getVisibility());
|
|
|
|
if (Subtarget->isTargetELF())
|
|
O << "\t.type " << name << ",%object\n";
|
|
|
|
const Section *TheSection = TAI->SectionForGlobal(GVar);
|
|
SwitchToSection(TheSection);
|
|
|
|
if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
|
|
// Don't put things that should go in the cstring section into "comm".
|
|
!TheSection->hasFlag(SectionFlags::Strings)) {
|
|
if (GVar->hasExternalLinkage()) {
|
|
if (const char *Directive = TAI->getZeroFillDirective()) {
|
|
O << "\t.globl\t" << name << "\n";
|
|
O << Directive << "__DATA, __common, " << name << ", "
|
|
<< Size << ", " << Align << "\n";
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
|
|
if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
|
|
|
|
if (isDarwin) {
|
|
if (GVar->hasLocalLinkage()) {
|
|
O << TAI->getLCOMMDirective() << name << "," << Size
|
|
<< ',' << Align;
|
|
} else if (GVar->hasCommonLinkage()) {
|
|
O << TAI->getCOMMDirective() << name << "," << Size
|
|
<< ',' << Align;
|
|
} else {
|
|
SwitchToSection(TAI->SectionForGlobal(GVar));
|
|
O << "\t.globl " << name << '\n'
|
|
<< TAI->getWeakDefDirective() << name << '\n';
|
|
EmitAlignment(Align, GVar);
|
|
O << name << ":";
|
|
if (VerboseAsm) {
|
|
O << "\t\t\t\t" << TAI->getCommentString() << ' ';
|
|
PrintUnmangledNameSafely(GVar, O);
|
|
}
|
|
O << '\n';
|
|
EmitGlobalConstant(C);
|
|
return;
|
|
}
|
|
} else if (TAI->getLCOMMDirective() != NULL) {
|
|
if (GVar->hasLocalLinkage()) {
|
|
O << TAI->getLCOMMDirective() << name << "," << Size;
|
|
} else {
|
|
O << TAI->getCOMMDirective() << name << "," << Size;
|
|
if (TAI->getCOMMDirectiveTakesAlignment())
|
|
O << ',' << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
|
|
}
|
|
} else {
|
|
if (GVar->hasLocalLinkage())
|
|
O << "\t.local\t" << name << "\n";
|
|
O << TAI->getCOMMDirective() << name << "," << Size;
|
|
if (TAI->getCOMMDirectiveTakesAlignment())
|
|
O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
|
|
}
|
|
if (VerboseAsm) {
|
|
O << "\t\t" << TAI->getCommentString() << " ";
|
|
PrintUnmangledNameSafely(GVar, O);
|
|
}
|
|
O << "\n";
|
|
return;
|
|
}
|
|
}
|
|
|
|
switch (GVar->getLinkage()) {
|
|
case GlobalValue::CommonLinkage:
|
|
case GlobalValue::LinkOnceAnyLinkage:
|
|
case GlobalValue::LinkOnceODRLinkage:
|
|
case GlobalValue::WeakAnyLinkage:
|
|
case GlobalValue::WeakODRLinkage:
|
|
if (isDarwin) {
|
|
O << "\t.globl " << name << "\n"
|
|
<< "\t.weak_definition " << name << "\n";
|
|
} else {
|
|
O << "\t.weak " << name << "\n";
|
|
}
|
|
break;
|
|
case GlobalValue::AppendingLinkage:
|
|
// FIXME: appending linkage variables should go into a section of
|
|
// their name or something. For now, just emit them as external.
|
|
case GlobalValue::ExternalLinkage:
|
|
O << "\t.globl " << name << "\n";
|
|
break;
|
|
case GlobalValue::PrivateLinkage:
|
|
case GlobalValue::LinkerPrivateLinkage:
|
|
case GlobalValue::InternalLinkage:
|
|
break;
|
|
default:
|
|
llvm_unreachable("Unknown linkage type!");
|
|
}
|
|
|
|
EmitAlignment(Align, GVar);
|
|
O << name << ":";
|
|
if (VerboseAsm) {
|
|
O << "\t\t\t\t" << TAI->getCommentString() << " ";
|
|
PrintUnmangledNameSafely(GVar, O);
|
|
}
|
|
O << "\n";
|
|
if (TAI->hasDotTypeDotSizeDirective())
|
|
O << "\t.size " << name << ", " << Size << "\n";
|
|
|
|
EmitGlobalConstant(C);
|
|
O << '\n';
|
|
}
|
|
|
|
|
|
bool ARMAsmPrinter::doFinalization(Module &M) {
|
|
if (Subtarget->isTargetDarwin()) {
|
|
SwitchToDataSection("");
|
|
|
|
O << '\n';
|
|
// Output stubs for dynamically-linked functions
|
|
for (StringMap<FnStubInfo>::iterator I = FnStubs.begin(), E = FnStubs.end();
|
|
I != E; ++I) {
|
|
const FnStubInfo &Info = I->second;
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
SwitchToTextSection(".section __TEXT,__picsymbolstub4,symbol_stubs,"
|
|
"none,16", 0);
|
|
else
|
|
SwitchToTextSection(".section __TEXT,__symbol_stub4,symbol_stubs,"
|
|
"none,12", 0);
|
|
|
|
EmitAlignment(2);
|
|
O << "\t.code\t32\n";
|
|
|
|
O << Info.Stub << ":\n";
|
|
O << "\t.indirect_symbol " << I->getKeyData() << '\n';
|
|
O << "\tldr ip, " << Info.SLP << '\n';
|
|
if (TM.getRelocationModel() == Reloc::PIC_) {
|
|
O << Info.SCV << ":\n";
|
|
O << "\tadd ip, pc, ip\n";
|
|
}
|
|
O << "\tldr pc, [ip, #0]\n";
|
|
O << Info.SLP << ":\n";
|
|
O << "\t.long\t" << Info.LazyPtr;
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
O << "-(" << Info.SCV << "+8)";
|
|
O << '\n';
|
|
|
|
SwitchToDataSection(".lazy_symbol_pointer", 0);
|
|
O << Info.LazyPtr << ":\n";
|
|
O << "\t.indirect_symbol " << I->getKeyData() << "\n";
|
|
O << "\t.long\tdyld_stub_binding_helper\n";
|
|
}
|
|
O << '\n';
|
|
|
|
// Output non-lazy-pointers for external and common global variables.
|
|
if (!GVNonLazyPtrs.empty()) {
|
|
SwitchToDataSection("\t.non_lazy_symbol_pointer", 0);
|
|
for (StringMap<std::string>::iterator I = GVNonLazyPtrs.begin(),
|
|
E = GVNonLazyPtrs.end(); I != E; ++I) {
|
|
O << I->second << ":\n";
|
|
O << "\t.indirect_symbol " << I->getKeyData() << "\n";
|
|
O << "\t.long\t0\n";
|
|
}
|
|
}
|
|
|
|
if (!HiddenGVNonLazyPtrs.empty()) {
|
|
SwitchToSection(TAI->getDataSection());
|
|
for (StringMap<std::string>::iterator I = HiddenGVNonLazyPtrs.begin(),
|
|
E = HiddenGVNonLazyPtrs.end(); I != E; ++I) {
|
|
EmitAlignment(2);
|
|
O << I->second << ":\n";
|
|
O << "\t.long " << I->getKeyData() << "\n";
|
|
}
|
|
}
|
|
|
|
|
|
// Funny Darwin hack: This flag tells the linker that no global symbols
|
|
// contain code that falls through to other global symbols (e.g. the obvious
|
|
// implementation of multiple entry points). If this doesn't occur, the
|
|
// linker can safely perform dead code stripping. Since LLVM never
|
|
// generates code that does this, it is always safe to set.
|
|
O << "\t.subsections_via_symbols\n";
|
|
}
|
|
|
|
return AsmPrinter::doFinalization(M);
|
|
}
|
|
|
|
/// createARMCodePrinterPass - Returns a pass that prints the ARM
|
|
/// assembly code for a MachineFunction to the given output stream,
|
|
/// using the given target machine description. This should work
|
|
/// regardless of whether the function is in SSA form.
|
|
///
|
|
FunctionPass *llvm::createARMCodePrinterPass(formatted_raw_ostream &o,
|
|
TargetMachine &tm,
|
|
bool verbose) {
|
|
return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), verbose);
|
|
}
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeARMAsmPrinter() {
|
|
TargetRegistry::RegisterAsmPrinter(TheARMTarget, createARMCodePrinterPass);
|
|
TargetRegistry::RegisterAsmPrinter(TheThumbTarget, createARMCodePrinterPass);
|
|
}
|