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Summary: start to do simple constants finish simplestore add test case format Merge branch 'master' into 1756_8 Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel Merge branch 'master' into 1756_8 Add basic functionality for assignment of ints. This creates a lot of core infrastructure in which to add, with little effort, quite a bit more to mips fast-isel in progress finish integer materialize test cases test cases in progress Finish up fast-isel materialize for ints. Finish materialize for ints test cases simplestorei.ll Merge branch 'master' into 1756_8 fix fp constants for fast-isel Merge branch '1758_1' of dmz-portal.mips.com:llvm into 1758_1 in progress lastest for fp materialization clean up Merge branch 'master' into 1758_1 formatting add test case finish test case Merge branch 'master' into 1758_2 Test Plan: simplestore.ll simplestore.ll Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210414 91177308-0d34-0410-b5e6-96231b3b80d8
315 lines
9.5 KiB
C++
315 lines
9.5 KiB
C++
//===-- MipsastISel.cpp - Mips FastISel implementation
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//---------------------===//
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLibraryInfo.h"
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#include "MipsRegisterInfo.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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using namespace llvm;
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namespace {
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// All possible address modes.
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typedef struct Address {
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enum { RegBase, FrameIndexBase } BaseType;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int64_t Offset;
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// Innocuous defaults for our address.
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Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
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} Address;
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class MipsFastISel final : public FastISel {
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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Module &M;
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const MipsSubtarget &Subtarget;
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MipsFunctionInfo *MFI;
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// Convenience variables to avoid some queries.
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LLVMContext *Context;
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bool TargetSupported;
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public:
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explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo)
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: FastISel(funcInfo, libInfo),
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M(const_cast<Module &>(*funcInfo.Fn->getParent())),
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TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
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TLI(*TM.getTargetLowering()),
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Subtarget(TM.getSubtarget<MipsSubtarget>()) {
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MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
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Context = &funcInfo.Fn->getContext();
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TargetSupported = ((Subtarget.getRelocationModel() == Reloc::PIC_) &&
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(Subtarget.hasMips32r2() && (Subtarget.isABI_O32())));
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}
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bool TargetSelectInstruction(const Instruction *I) override;
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unsigned TargetMaterializeConstant(const Constant *C) override;
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bool ComputeAddress(const Value *Obj, Address &Addr);
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private:
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bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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bool SelectRet(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
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unsigned MaterializeInt(const Constant *C, MVT VT);
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unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
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// for some reason, this default is not generated by tablegen
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// so we explicitly generate it here.
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//
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unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
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unsigned Op0, bool Op0IsKill, uint64_t imm1,
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uint64_t imm2, unsigned Op3, bool Op3IsKill) {
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return 0;
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}
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MachineInstrBuilder EmitInst(unsigned Opc) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
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}
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MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
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return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
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DstReg);
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}
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MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
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unsigned MemReg, int64_t MemOffset) {
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return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
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}
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#include "MipsGenFastISel.inc"
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};
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bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
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EVT evt = TLI.getValueType(Ty, true);
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// Only handle simple types.
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if (evt == MVT::Other || !evt.isSimple())
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return false;
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VT = evt.getSimpleVT();
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// Handle all legal types, i.e. a register that will directly hold this
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// value.
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return TLI.isTypeLegal(VT);
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}
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bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
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if (isTypeLegal(Ty, VT))
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return true;
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// We will extend this in a later patch:
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// If this is a type than can be sign or zero-extended to a basic operation
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// go ahead and accept it now.
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return false;
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}
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bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
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// This construct looks a big awkward but it is how other ports handle this
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// and as this function is more fully completed, these cases which
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// return false will have additional code in them.
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//
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if (isa<Instruction>(Obj))
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return false;
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else if (isa<ConstantExpr>(Obj))
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return false;
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Addr.Base.Reg = getRegForValue(Obj);
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return Addr.Base.Reg != 0;
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}
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// Materialize a constant into a register, and return the register
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// number (or zero if we failed to handle it).
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unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) {
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EVT CEVT = TLI.getValueType(C->getType(), true);
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// Only handle simple types.
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if (!CEVT.isSimple())
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return 0;
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MVT VT = CEVT.getSimpleVT();
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if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return MaterializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return MaterializeGV(GV, VT);
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else if (isa<ConstantInt>(C))
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return MaterializeInt(C, VT);
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return 0;
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}
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bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment) {
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//
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// more cases will be handled here in following patches.
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//
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if (VT == MVT::i32)
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EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
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else if (VT == MVT::f32)
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EmitInstStore(Mips::SWC1, SrcReg, Addr.Base.Reg, Addr.Offset);
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else if (VT == MVT::f64)
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EmitInstStore(Mips::SDC1, SrcReg, Addr.Base.Reg, Addr.Offset);
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else
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return false;
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return true;
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}
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bool MipsFastISel::SelectStore(const Instruction *I) {
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Value *Op0 = I->getOperand(0);
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unsigned SrcReg = 0;
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// Atomic stores need special handling.
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if (cast<StoreInst>(I)->isAtomic())
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return false;
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// Verify we have a legal type before going any further.
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MVT VT;
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if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
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return false;
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// Get the value to be stored into a register.
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SrcReg = getRegForValue(Op0);
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if (SrcReg == 0)
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return false;
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// See if we can handle this address.
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Address Addr;
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if (!ComputeAddress(I->getOperand(1), Addr))
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return false;
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if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
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return false;
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return true;
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}
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bool MipsFastISel::SelectRet(const Instruction *I) {
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const ReturnInst *Ret = cast<ReturnInst>(I);
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if (!FuncInfo.CanLowerReturn)
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return false;
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if (Ret->getNumOperands() > 0) {
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return false;
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}
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EmitInst(Mips::RetRA);
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return true;
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}
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bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
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if (!TargetSupported)
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return false;
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switch (I->getOpcode()) {
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default:
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break;
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case Instruction::Store:
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return SelectStore(I);
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case Instruction::Ret:
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return SelectRet(I);
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}
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return false;
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}
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}
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unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
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int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
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if (VT == MVT::f32) {
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const TargetRegisterClass *RC = &Mips::FGR32RegClass;
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unsigned DestReg = createResultReg(RC);
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unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
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EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
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return DestReg;
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} else if (VT == MVT::f64) {
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const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
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unsigned DestReg = createResultReg(RC);
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unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
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unsigned TempReg2 =
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Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
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EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
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return DestReg;
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}
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return 0;
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}
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unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
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// For now 32-bit only.
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if (VT != MVT::i32)
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return 0;
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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unsigned DestReg = createResultReg(RC);
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const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
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bool IsThreadLocal = GVar && GVar->isThreadLocal();
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// TLS not supported at this time.
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if (IsThreadLocal)
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return 0;
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EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress(
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GV, 0, MipsII::MO_GOT);
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return DestReg;
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}
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unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
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if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
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return 0;
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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const ConstantInt *CI = cast<ConstantInt>(C);
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int64_t Imm;
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if (CI->isNegative())
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Imm = CI->getSExtValue();
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else
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Imm = CI->getZExtValue();
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return Materialize32BitInt(Imm, RC);
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}
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unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
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const TargetRegisterClass *RC) {
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unsigned ResultReg = createResultReg(RC);
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if (isInt<16>(Imm)) {
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unsigned Opc = Mips::ADDiu;
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EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
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return ResultReg;
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} else if (isUInt<16>(Imm)) {
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EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
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return ResultReg;
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}
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unsigned Lo = Imm & 0xFFFF;
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unsigned Hi = (Imm >> 16) & 0xFFFF;
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if (Lo) {
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// Both Lo and Hi have nonzero bits.
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unsigned TmpReg = createResultReg(RC);
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EmitInst(Mips::LUi, TmpReg).addImm(Hi);
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EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
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} else {
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EmitInst(Mips::LUi, ResultReg).addImm(Hi);
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}
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return ResultReg;
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}
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namespace llvm {
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FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo) {
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return new MipsFastISel(funcInfo, libInfo);
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}
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}
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