mirror of
https://github.com/c64scene-ar/llvm-6502.git
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108934c65d
X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
2484 lines
118 KiB
TableGen
2484 lines
118 KiB
TableGen
//====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86-64 instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand Definitions.
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//
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// 64-bits but only 32 bits are significant.
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def i64i32imm : Operand<i64>;
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// 64-bits but only 32 bits are significant, and those bits are treated as being
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// pc relative.
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def i64i32imm_pcrel : Operand<i64> {
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let PrintMethod = "print_pcrel_imm";
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}
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// 64-bits but only 8 bits are significant.
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def i64i8imm : Operand<i64> {
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let ParserMatchClass = ImmSExt8AsmOperand;
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}
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def lea64mem : Operand<i64> {
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let PrintMethod = "printlea64mem";
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let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
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let ParserMatchClass = X86MemAsmOperand;
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}
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def lea64_32mem : Operand<i32> {
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let PrintMethod = "printlea64_32mem";
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let AsmOperandLowerMethod = "lower_lea64_32mem";
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let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
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let ParserMatchClass = X86MemAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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// Complex Pattern Definitions.
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//
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def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
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[add, sub, mul, X86mul_imm, shl, or, frameindex,
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X86WrapperRIP], []>;
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def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
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[tglobaltlsaddr], []>;
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//===----------------------------------------------------------------------===//
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// Pattern fragments.
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//
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def i64immSExt8 : PatLeaf<(i64 imm), [{
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// i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
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// sign extended field.
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return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
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}]>;
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def i64immSExt32 : PatLeaf<(i64 imm), [{
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// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// sign extended field.
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return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
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}]>;
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def i64immZExt32 : PatLeaf<(i64 imm), [{
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// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// unsignedsign extended field.
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return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
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}]>;
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def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
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def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
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def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
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def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
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def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
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def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
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def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
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def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
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def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
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def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
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def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
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//===----------------------------------------------------------------------===//
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// Instruction list...
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//
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// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber EFLAGS.
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let Defs = [RSP, EFLAGS], Uses = [RSP] in {
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def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(X86callseq_start timm:$amt)]>,
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Requires<[In64BitMode]>;
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def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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"#ADJCALLSTACKUP",
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[(X86callseq_end timm:$amt1, timm:$amt2)]>,
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Requires<[In64BitMode]>;
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}
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// Interrupt Instructions
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def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [RSP] in {
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// NOTE: this pattern doesn't match "X86call imm", because we do not know
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// that the offset between an arbitrary immediate and the call will fit in
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// the 32-bit pcrel field that we have.
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def CALL64pcrel32 : Ii32<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst, variable_ops),
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"call{q}\t$dst", []>,
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Requires<[In64BitMode, NotWin64]>;
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def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
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"call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
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Requires<[NotWin64]>;
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def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
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"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
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Requires<[NotWin64]>;
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def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
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"lcall{q}\t{*}$dst", []>;
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}
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// FIXME: We need to teach codegen about single list of call-clobbered
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// registers.
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
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Uses = [RSP] in {
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def WINCALL64pcrel32 : I<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst, variable_ops),
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"call\t$dst", []>,
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Requires<[IsWin64]>;
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def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
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"call\t{*}$dst",
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[(X86call GR64:$dst)]>, Requires<[IsWin64]>;
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def WINCALL64m : I<0xFF, MRM2m, (outs),
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(ins i64mem:$dst, variable_ops), "call\t{*}$dst",
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[(X86call (loadi64 addr:$dst))]>,
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Requires<[IsWin64]>;
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}
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
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variable_ops),
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"#TC_RETURN $dst $offset",
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[]>;
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
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variable_ops),
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"#TC_RETURN $dst $offset",
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[]>;
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
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"jmp{q}\t{*}$dst # TAILCALL",
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[]>;
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// Branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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"jmp{q}\t$dst", []>;
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def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
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[(brind GR64:$dst)]>;
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def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
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[(brind (loadi64 addr:$dst))]>;
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def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
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"ljmp{q}\t{*}$dst", []>;
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}
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//===----------------------------------------------------------------------===//
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// EH Pseudo Instructions
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//
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1 in {
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def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
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"ret\t#eh_return, addr: $addr",
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[(X86ehret GR64:$addr)]>;
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions...
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//
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def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
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def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
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let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
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def LEAVE64 : I<0xC9, RawFrm,
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(outs), (ins), "leave", []>;
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let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
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let mayLoad = 1 in {
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def POP64r : I<0x58, AddRegFrm,
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(outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
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def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
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def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
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}
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let mayStore = 1 in {
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def PUSH64r : I<0x50, AddRegFrm,
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(outs), (ins GR64:$reg), "push{q}\t$reg", []>;
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def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
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def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
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}
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}
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let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
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def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
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"push{q}\t$imm", []>;
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def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
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"push{q}\t$imm", []>;
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def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
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"push{q}\t$imm", []>;
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}
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let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
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def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf{q}", []>, REX_W;
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let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
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def PUSHFQ64 : I<0x9C, RawFrm, (outs), (ins), "pushf{q}", []>;
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def LEA64_32r : I<0x8D, MRMSrcMem,
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(outs GR32:$dst), (ins lea64_32mem:$src),
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"lea{l}\t{$src|$dst}, {$dst|$src}",
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[(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
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let isReMaterializable = 1 in
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def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
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"lea{q}\t{$src|$dst}, {$dst|$src}",
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[(set GR64:$dst, lea64addr:$src)]>;
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let isTwoAddress = 1 in
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def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
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"bswap{q}\t$dst",
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[(set GR64:$dst, (bswap GR64:$src))]>, TB;
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// Bit scan instructions.
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let Defs = [EFLAGS] in {
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def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"bsf{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
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def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsf{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
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(implicit EFLAGS)]>, TB;
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def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"bsr{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
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def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsr{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
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(implicit EFLAGS)]>, TB;
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} // Defs = [EFLAGS]
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// Repeat string ops
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let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
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def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
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[(X86rep_movs i64)]>, REP;
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let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
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def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
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[(X86rep_stos i64)]>, REP;
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def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
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def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
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// Fast system-call instructions
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def SYSEXIT64 : RI<0x35, RawFrm,
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(outs), (ins), "sysexit", []>, TB;
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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//
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let neverHasSideEffects = 1 in
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def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
|
|
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
|
|
"movabs{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, imm:$src)]>;
|
|
def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, i64immSExt32:$src)]>;
|
|
}
|
|
|
|
def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
|
|
def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (load addr:$src))]>;
|
|
|
|
def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}",
|
|
[(store GR64:$src, addr:$dst)]>;
|
|
def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}",
|
|
[(store i64immSExt32:$src, addr:$dst)]>;
|
|
|
|
def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
|
|
"mov{q}\t{$src, %rax|%rax, $src}", []>;
|
|
def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
|
|
"mov{q}\t{$src, %rax|%rax, $src}", []>;
|
|
def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
|
|
"mov{q}\t{%rax, $dst|$dst, %rax}", []>;
|
|
def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
|
|
"mov{q}\t{%rax, $dst|$dst, %rax}", []>;
|
|
|
|
// Moves to and from segment registers
|
|
def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
|
def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
|
def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
|
def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
// Moves to and from debug registers
|
|
def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
// Moves to and from control registers
|
|
def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
|
|
"mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
// Sign/Zero extenders
|
|
|
|
// MOVSX64rr8 always has a REX prefix and it has an 8-bit register
|
|
// operand, which makes it a rare instruction with an 8-bit register
|
|
// operand that can never access an h register. If support for h registers
|
|
// were generalized, this would require a special register class.
|
|
def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
|
|
"movs{bq|x}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (sext GR8:$src))]>, TB;
|
|
def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
|
|
"movs{bq|x}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
|
|
def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
|
|
"movs{wq|x}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (sext GR16:$src))]>, TB;
|
|
def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
|
|
"movs{wq|x}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
|
|
def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
|
|
"movs{lq|xd}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (sext GR32:$src))]>;
|
|
def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
|
|
"movs{lq|xd}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
|
|
|
|
// movzbq and movzwq encodings for the disassembler
|
|
def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
|
|
"movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
|
|
"movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
|
|
"movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
|
|
"movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
// Use movzbl instead of movzbq when the destination is a register; it's
|
|
// equivalent due to implicit zero-extending, and it has a smaller encoding.
|
|
def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
|
|
"", [(set GR64:$dst, (zext GR8:$src))]>, TB;
|
|
def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
|
|
"", [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
|
|
// Use movzwl instead of movzwq when the destination is a register; it's
|
|
// equivalent due to implicit zero-extending, and it has a smaller encoding.
|
|
def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
|
|
"", [(set GR64:$dst, (zext GR16:$src))]>, TB;
|
|
def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
|
|
"", [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
|
|
|
|
// There's no movzlq instruction, but movl can be used for this purpose, using
|
|
// implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
|
|
// extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
|
|
// zero-extension, however this isn't possible when the 32-bit value is
|
|
// defined by a truncate or is copied from something where the high bits aren't
|
|
// necessarily all zero. In such cases, we fall back to these explicit zext
|
|
// instructions.
|
|
def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
|
|
"", [(set GR64:$dst, (zext GR32:$src))]>;
|
|
def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
|
|
"", [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
|
|
|
|
// Any instruction that defines a 32-bit result leaves the high half of the
|
|
// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
|
|
// be copying from a truncate. And x86's cmov doesn't do anything if the
|
|
// condition is false. But any other 32-bit operation will zero-extend
|
|
// up to 64 bits.
|
|
def def32 : PatLeaf<(i32 GR32:$src), [{
|
|
return N->getOpcode() != ISD::TRUNCATE &&
|
|
N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
|
|
N->getOpcode() != ISD::CopyFromReg &&
|
|
N->getOpcode() != X86ISD::CMOV;
|
|
}]>;
|
|
|
|
// In the case of a 32-bit def that is known to implicitly zero-extend,
|
|
// we can use a SUBREG_TO_REG.
|
|
def : Pat<(i64 (zext def32:$src)),
|
|
(SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
|
|
|
|
let neverHasSideEffects = 1 in {
|
|
let Defs = [RAX], Uses = [EAX] in
|
|
def CDQE : RI<0x98, RawFrm, (outs), (ins),
|
|
"{cltq|cdqe}", []>; // RAX = signext(EAX)
|
|
|
|
let Defs = [RAX,RDX], Uses = [RAX] in
|
|
def CQO : RI<0x99, RawFrm, (outs), (ins),
|
|
"{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arithmetic Instructions...
|
|
//
|
|
|
|
let Defs = [EFLAGS] in {
|
|
|
|
def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
|
|
"add{q}\t{$src, %rax|%rax, $src}", []>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
let isConvertibleToThreeAddress = 1 in {
|
|
let isCommutable = 1 in
|
|
// Register-Register Addition
|
|
def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"add{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
|
|
// Register-Integer Addition
|
|
def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i8imm:$src2),
|
|
"add{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i32imm:$src2),
|
|
"add{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
} // isConvertibleToThreeAddress
|
|
|
|
// Register-Memory Addition
|
|
def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64mem:$src2),
|
|
"add{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
|
|
(implicit EFLAGS)]>;
|
|
|
|
// Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
|
|
// differently encoded.
|
|
def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"add{l}\t{$src2, $dst|$dst, $src2}", []>;
|
|
|
|
} // isTwoAddress
|
|
|
|
// Memory-Register Addition
|
|
def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
|
"add{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (add (load addr:$dst), GR64:$src2), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
|
|
"add{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
|
|
"add{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
let Uses = [EFLAGS] in {
|
|
|
|
def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
|
|
"adc{q}\t{$src, %rax|%rax, $src}", []>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
let isCommutable = 1 in
|
|
def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"adc{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
|
|
|
|
def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"adc{q}\t{$src2, $dst|$dst, $src2}", []>;
|
|
|
|
def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
|
|
(ins GR64:$src1, i64mem:$src2),
|
|
"adc{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
|
|
|
|
def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i8imm:$src2),
|
|
"adc{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
|
|
def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i32imm:$src2),
|
|
"adc{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
|
|
} // isTwoAddress
|
|
|
|
def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
|
"adc{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
|
|
def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
|
|
"adc{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (adde (load addr:$dst), i64immSExt8:$src2),
|
|
addr:$dst)]>;
|
|
def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
|
|
"adc{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (adde (load addr:$dst), i64immSExt8:$src2),
|
|
addr:$dst)]>;
|
|
} // Uses = [EFLAGS]
|
|
|
|
let isTwoAddress = 1 in {
|
|
// Register-Register Subtraction
|
|
def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
|
|
def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}", []>;
|
|
|
|
// Register-Memory Subtraction
|
|
def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64mem:$src2),
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
|
|
(implicit EFLAGS)]>;
|
|
|
|
// Register-Integer Subtraction
|
|
def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i8imm:$src2),
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i32imm:$src2),
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
} // isTwoAddress
|
|
|
|
def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
|
|
"sub{q}\t{$src, %rax|%rax, $src}", []>;
|
|
|
|
// Memory-Register Subtraction
|
|
def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
// Memory-Integer Subtraction
|
|
def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (sub (load addr:$dst), i64immSExt8:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (sub (load addr:$dst), i64immSExt32:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
let Uses = [EFLAGS] in {
|
|
let isTwoAddress = 1 in {
|
|
def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"sbb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
|
|
|
|
def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
|
|
|
|
def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64mem:$src2),
|
|
"sbb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
|
|
|
|
def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i8imm:$src2),
|
|
"sbb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
|
|
def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i32imm:$src2),
|
|
"sbb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
|
|
} // isTwoAddress
|
|
|
|
def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
|
|
"sbb{q}\t{$src, %rax|%rax, $src}", []>;
|
|
|
|
def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
|
"sbb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
|
|
def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
|
|
"sbb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
|
|
def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
|
|
"sbb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
|
|
} // Uses = [EFLAGS]
|
|
} // Defs = [EFLAGS]
|
|
|
|
// Unsigned multiplication
|
|
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
|
|
def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
|
|
"mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
|
|
let mayLoad = 1 in
|
|
def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
|
|
"mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
|
|
|
|
// Signed multiplication
|
|
def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
|
|
"imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
|
|
let mayLoad = 1 in
|
|
def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
|
|
"imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
|
|
}
|
|
|
|
let Defs = [EFLAGS] in {
|
|
let isTwoAddress = 1 in {
|
|
let isCommutable = 1 in
|
|
// Register-Register Signed Integer Multiplication
|
|
def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"imul{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
|
|
(implicit EFLAGS)]>, TB;
|
|
|
|
// Register-Memory Signed Integer Multiplication
|
|
def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64mem:$src2),
|
|
"imul{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
|
|
(implicit EFLAGS)]>, TB;
|
|
} // isTwoAddress
|
|
|
|
// Suprisingly enough, these are not two address instructions!
|
|
|
|
// Register-Integer Signed Integer Multiplication
|
|
def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
|
|
(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
|
|
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
|
|
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
|
|
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
|
|
// Memory-Integer Signed Integer Multiplication
|
|
def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
|
|
(outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
|
|
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set GR64:$dst, (mul (load addr:$src1),
|
|
i64immSExt8:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
|
|
(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
|
|
"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set GR64:$dst, (mul (load addr:$src1),
|
|
i64immSExt32:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
} // Defs = [EFLAGS]
|
|
|
|
// Unsigned division / remainder
|
|
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
|
|
// RDX:RAX/r64 = RAX,RDX
|
|
def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
|
|
"div{q}\t$src", []>;
|
|
// Signed division / remainder
|
|
// RDX:RAX/r64 = RAX,RDX
|
|
def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
|
|
"idiv{q}\t$src", []>;
|
|
let mayLoad = 1 in {
|
|
// RDX:RAX/[mem64] = RAX,RDX
|
|
def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
|
|
"div{q}\t$src", []>;
|
|
// RDX:RAX/[mem64] = RAX,RDX
|
|
def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
|
|
"idiv{q}\t$src", []>;
|
|
}
|
|
}
|
|
|
|
// Unary instructions
|
|
let Defs = [EFLAGS], CodeSize = 2 in {
|
|
let isTwoAddress = 1 in
|
|
def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
|
|
[(set GR64:$dst, (ineg GR64:$src)),
|
|
(implicit EFLAGS)]>;
|
|
def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
|
|
[(store (ineg (loadi64 addr:$dst)), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
|
|
def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
|
|
[(set GR64:$dst, (add GR64:$src, 1)),
|
|
(implicit EFLAGS)]>;
|
|
def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
|
|
[(store (add (loadi64 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
|
|
def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
|
|
[(set GR64:$dst, (add GR64:$src, -1)),
|
|
(implicit EFLAGS)]>;
|
|
def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
|
|
[(store (add (loadi64 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
// In 64-bit mode, single byte INC and DEC cannot be encoded.
|
|
let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
|
|
// Can transform into LEA.
|
|
def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
|
|
"inc{w}\t$dst",
|
|
[(set GR16:$dst, (add GR16:$src, 1)),
|
|
(implicit EFLAGS)]>,
|
|
OpSize, Requires<[In64BitMode]>;
|
|
def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
|
|
"inc{l}\t$dst",
|
|
[(set GR32:$dst, (add GR32:$src, 1)),
|
|
(implicit EFLAGS)]>,
|
|
Requires<[In64BitMode]>;
|
|
def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
|
|
"dec{w}\t$dst",
|
|
[(set GR16:$dst, (add GR16:$src, -1)),
|
|
(implicit EFLAGS)]>,
|
|
OpSize, Requires<[In64BitMode]>;
|
|
def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
|
|
"dec{l}\t$dst",
|
|
[(set GR32:$dst, (add GR32:$src, -1)),
|
|
(implicit EFLAGS)]>,
|
|
Requires<[In64BitMode]>;
|
|
} // isConvertibleToThreeAddress
|
|
|
|
// These are duplicates of their 32-bit counterparts. Only needed so X86 knows
|
|
// how to unfold them.
|
|
let isTwoAddress = 0, CodeSize = 2 in {
|
|
def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
|
|
[(store (add (loadi16 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)]>,
|
|
OpSize, Requires<[In64BitMode]>;
|
|
def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
|
|
[(store (add (loadi32 addr:$dst), 1), addr:$dst),
|
|
(implicit EFLAGS)]>,
|
|
Requires<[In64BitMode]>;
|
|
def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
|
|
[(store (add (loadi16 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)]>,
|
|
OpSize, Requires<[In64BitMode]>;
|
|
def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
|
|
[(store (add (loadi32 addr:$dst), -1), addr:$dst),
|
|
(implicit EFLAGS)]>,
|
|
Requires<[In64BitMode]>;
|
|
}
|
|
} // Defs = [EFLAGS], CodeSize
|
|
|
|
|
|
let Defs = [EFLAGS] in {
|
|
// Shift instructions
|
|
let isTwoAddress = 1 in {
|
|
let Uses = [CL] in
|
|
def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
|
|
"shl{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(set GR64:$dst, (shl GR64:$src, CL))]>;
|
|
let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
|
|
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i8imm:$src2),
|
|
"shl{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
|
|
// NOTE: We don't include patterns for shifts of a register by one, because
|
|
// 'add reg,reg' is cheaper.
|
|
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
|
|
"shl{q}\t$dst", []>;
|
|
} // isTwoAddress
|
|
|
|
let Uses = [CL] in
|
|
def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
|
|
"shl{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
|
|
def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
|
|
"shl{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|
def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
|
|
"shl{q}\t$dst",
|
|
[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
let Uses = [CL] in
|
|
def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
|
|
"shr{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(set GR64:$dst, (srl GR64:$src, CL))]>;
|
|
def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
|
|
"shr{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
|
|
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
|
|
"shr{q}\t$dst",
|
|
[(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
|
|
} // isTwoAddress
|
|
|
|
let Uses = [CL] in
|
|
def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
|
|
"shr{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
|
|
def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
|
|
"shr{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|
def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
|
|
"shr{q}\t$dst",
|
|
[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
let Uses = [CL] in
|
|
def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
|
|
"sar{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(set GR64:$dst, (sra GR64:$src, CL))]>;
|
|
def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i8imm:$src2),
|
|
"sar{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
|
|
def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
|
|
"sar{q}\t$dst",
|
|
[(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
|
|
} // isTwoAddress
|
|
|
|
let Uses = [CL] in
|
|
def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
|
|
"sar{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
|
|
def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
|
|
"sar{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|
def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
|
|
"sar{q}\t$dst",
|
|
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
|
|
|
// Rotate instructions
|
|
|
|
let isTwoAddress = 1 in {
|
|
def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src),
|
|
"rcl{q}\t{1, $dst|$dst, 1}", []>;
|
|
def RCL64m1 : RI<0xD1, MRM2m, (outs i64mem:$dst), (ins i64mem:$src),
|
|
"rcl{q}\t{1, $dst|$dst, 1}", []>;
|
|
let Uses = [CL] in {
|
|
def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src),
|
|
"rcl{q}\t{%cl, $dst|$dst, CL}", []>;
|
|
def RCL64mCL : RI<0xD3, MRM2m, (outs i64mem:$dst), (ins i64mem:$src),
|
|
"rcl{q}\t{%cl, $dst|$dst, CL}", []>;
|
|
}
|
|
def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
|
|
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|
def RCL64mi : RIi8<0xC1, MRM2m, (outs i64mem:$dst),
|
|
(ins i64mem:$src, i8imm:$cnt),
|
|
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|
|
|
def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
|
|
"rcr{q}\t{1, $dst|$dst, 1}", []>;
|
|
def RCR64m1 : RI<0xD1, MRM3m, (outs i64mem:$dst), (ins i64mem:$src),
|
|
"rcr{q}\t{1, $dst|$dst, 1}", []>;
|
|
let Uses = [CL] in {
|
|
def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src),
|
|
"rcr{q}\t{%cl, $dst|$dst, CL}", []>;
|
|
def RCR64mCL : RI<0xD3, MRM3m, (outs i64mem:$dst), (ins i64mem:$src),
|
|
"rcr{q}\t{%cl, $dst|$dst, CL}", []>;
|
|
}
|
|
def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
|
|
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|
def RCR64mi : RIi8<0xC1, MRM3m, (outs i64mem:$dst),
|
|
(ins i64mem:$src, i8imm:$cnt),
|
|
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|
}
|
|
|
|
let isTwoAddress = 1 in {
|
|
let Uses = [CL] in
|
|
def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
|
|
"rol{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(set GR64:$dst, (rotl GR64:$src, CL))]>;
|
|
def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i8imm:$src2),
|
|
"rol{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
|
|
def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
|
|
"rol{q}\t$dst",
|
|
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
|
|
} // isTwoAddress
|
|
|
|
let Uses = [CL] in
|
|
def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
|
|
"rol{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
|
|
def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
|
|
"rol{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|
def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
|
|
"rol{q}\t$dst",
|
|
[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
let Uses = [CL] in
|
|
def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
|
|
"ror{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(set GR64:$dst, (rotr GR64:$src, CL))]>;
|
|
def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i8imm:$src2),
|
|
"ror{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
|
|
def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
|
|
"ror{q}\t$dst",
|
|
[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
|
|
} // isTwoAddress
|
|
|
|
let Uses = [CL] in
|
|
def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
|
|
"ror{q}\t{%cl, $dst|$dst, %CL}",
|
|
[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
|
|
def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
|
|
"ror{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|
def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
|
|
"ror{q}\t$dst",
|
|
[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
|
|
|
|
// Double shift instructions (generalizations of rotate)
|
|
let isTwoAddress = 1 in {
|
|
let Uses = [CL] in {
|
|
def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
|
|
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
|
|
TB;
|
|
def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
|
|
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
|
|
TB;
|
|
}
|
|
|
|
let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
|
|
def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
|
|
(outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2, i8imm:$src3),
|
|
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
|
|
(i8 imm:$src3)))]>,
|
|
TB;
|
|
def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
|
|
(outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2, i8imm:$src3),
|
|
"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
|
|
(i8 imm:$src3)))]>,
|
|
TB;
|
|
} // isCommutable
|
|
} // isTwoAddress
|
|
|
|
let Uses = [CL] in {
|
|
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
|
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
|
|
[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
|
|
addr:$dst)]>, TB;
|
|
def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
|
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
|
|
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
|
|
addr:$dst)]>, TB;
|
|
}
|
|
def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
|
|
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
|
|
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[(store (X86shld (loadi64 addr:$dst), GR64:$src2,
|
|
(i8 imm:$src3)), addr:$dst)]>,
|
|
TB;
|
|
def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
|
|
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
|
|
"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
|
|
(i8 imm:$src3)), addr:$dst)]>,
|
|
TB;
|
|
} // Defs = [EFLAGS]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Logical Instructions...
|
|
//
|
|
|
|
let isTwoAddress = 1 , AddedComplexity = 15 in
|
|
def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
|
|
[(set GR64:$dst, (not GR64:$src))]>;
|
|
def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
|
|
[(store (not (loadi64 addr:$dst)), addr:$dst)]>;
|
|
|
|
let Defs = [EFLAGS] in {
|
|
def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
|
|
"and{q}\t{$src, %rax|%rax, $src}", []>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
let isCommutable = 1 in
|
|
def AND64rr : RI<0x21, MRMDestReg,
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"and{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"and{q}\t{$src2, $dst|$dst, $src2}", []>;
|
|
def AND64rm : RI<0x23, MRMSrcMem,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"and{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
|
|
(implicit EFLAGS)]>;
|
|
def AND64ri8 : RIi8<0x83, MRM4r,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
|
|
"and{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def AND64ri32 : RIi32<0x81, MRM4r,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
|
|
"and{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
} // isTwoAddress
|
|
|
|
def AND64mr : RI<0x21, MRMDestMem,
|
|
(outs), (ins i64mem:$dst, GR64:$src),
|
|
"and{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (and (load addr:$dst), GR64:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def AND64mi8 : RIi8<0x83, MRM4m,
|
|
(outs), (ins i64mem:$dst, i64i8imm :$src),
|
|
"and{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def AND64mi32 : RIi32<0x81, MRM4m,
|
|
(outs), (ins i64mem:$dst, i64i32imm:$src),
|
|
"and{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
let isCommutable = 1 in
|
|
def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"or{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"or{q}\t{$src2, $dst|$dst, $src2}", []>;
|
|
def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
|
|
(ins GR64:$src1, i64mem:$src2),
|
|
"or{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
|
|
(implicit EFLAGS)]>;
|
|
def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i8imm:$src2),
|
|
"or{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i32imm:$src2),
|
|
"or{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
} // isTwoAddress
|
|
|
|
def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
"or{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (or (load addr:$dst), GR64:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
|
|
"or{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
|
|
"or{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
|
|
"or{q}\t{$src, %rax|%rax, $src}", []>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
let isCommutable = 1 in
|
|
def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"xor{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"xor{q}\t{$src2, $dst|$dst, $src2}", []>;
|
|
def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64mem:$src2),
|
|
"xor{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
|
|
(implicit EFLAGS)]>;
|
|
def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64i8imm:$src2),
|
|
"xor{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def XOR64ri32 : RIi32<0x81, MRM6r,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
|
|
"xor{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
} // isTwoAddress
|
|
|
|
def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
"xor{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (xor (load addr:$dst), GR64:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
|
|
"xor{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
|
|
"xor{q}\t{$src, $dst|$dst, $src}",
|
|
[(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
|
|
(implicit EFLAGS)]>;
|
|
|
|
def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
|
|
"xor{q}\t{$src, %rax|%rax, $src}", []>;
|
|
|
|
} // Defs = [EFLAGS]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Comparison Instructions...
|
|
//
|
|
|
|
// Integer comparison
|
|
let Defs = [EFLAGS] in {
|
|
def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
|
|
"test{q}\t{$src, %rax|%rax, $src}", []>;
|
|
let isCommutable = 1 in
|
|
def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
"test{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp (and GR64:$src1, GR64:$src2), 0),
|
|
(implicit EFLAGS)]>;
|
|
def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
|
|
"test{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
|
|
(implicit EFLAGS)]>;
|
|
def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
|
|
(ins GR64:$src1, i64i32imm:$src2),
|
|
"test{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
|
|
(implicit EFLAGS)]>;
|
|
def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
|
|
(ins i64mem:$src1, i64i32imm:$src2),
|
|
"test{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
|
|
(implicit EFLAGS)]>;
|
|
|
|
|
|
def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
|
|
"cmp{q}\t{$src, %rax|%rax, $src}", []>;
|
|
def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp GR64:$src1, GR64:$src2),
|
|
(implicit EFLAGS)]>;
|
|
def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
"cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
|
|
def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp (loadi64 addr:$src1), GR64:$src2),
|
|
(implicit EFLAGS)]>;
|
|
def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
|
|
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp GR64:$src1, (loadi64 addr:$src2)),
|
|
(implicit EFLAGS)]>;
|
|
def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp GR64:$src1, i64immSExt8:$src2),
|
|
(implicit EFLAGS)]>;
|
|
def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
|
|
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp GR64:$src1, i64immSExt32:$src2),
|
|
(implicit EFLAGS)]>;
|
|
def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
|
|
(implicit EFLAGS)]>;
|
|
def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
|
|
(ins i64mem:$src1, i64i32imm:$src2),
|
|
"cmp{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
|
|
(implicit EFLAGS)]>;
|
|
} // Defs = [EFLAGS]
|
|
|
|
// Bit tests.
|
|
// TODO: BTC, BTR, and BTS
|
|
let Defs = [EFLAGS] in {
|
|
def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86bt GR64:$src1, GR64:$src2),
|
|
(implicit EFLAGS)]>, TB;
|
|
|
|
// Unlike with the register+register form, the memory+register form of the
|
|
// bt instruction does not ignore the high bits of the index. From ISel's
|
|
// perspective, this is pretty bizarre. Disable these instructions for now.
|
|
def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
|
// [(X86bt (loadi64 addr:$src1), GR64:$src2),
|
|
// (implicit EFLAGS)]
|
|
[]
|
|
>, TB;
|
|
|
|
def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86bt GR64:$src1, i64immSExt8:$src2),
|
|
(implicit EFLAGS)]>, TB;
|
|
// Note that these instructions don't need FastBTMem because that
|
|
// only applies when the other operand is in a register. When it's
|
|
// an immediate, bt is still fast.
|
|
def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
|
[(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
|
|
(implicit EFLAGS)]>, TB;
|
|
|
|
def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
|
|
def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
|
|
def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
|
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
|
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
|
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
|
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|
} // Defs = [EFLAGS]
|
|
|
|
// Conditional moves
|
|
let Uses = [EFLAGS], isTwoAddress = 1 in {
|
|
let isCommutable = 1 in {
|
|
def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_B, EFLAGS))]>, TB;
|
|
def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovae{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_AE, EFLAGS))]>, TB;
|
|
def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmove{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_E, EFLAGS))]>, TB;
|
|
def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovne{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_NE, EFLAGS))]>, TB;
|
|
def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovbe{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_BE, EFLAGS))]>, TB;
|
|
def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmova{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_A, EFLAGS))]>, TB;
|
|
def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovl{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_L, EFLAGS))]>, TB;
|
|
def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovge{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_GE, EFLAGS))]>, TB;
|
|
def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovle{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_LE, EFLAGS))]>, TB;
|
|
def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovg{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_G, EFLAGS))]>, TB;
|
|
def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovs{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_S, EFLAGS))]>, TB;
|
|
def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovns{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_NS, EFLAGS))]>, TB;
|
|
def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovp{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_P, EFLAGS))]>, TB;
|
|
def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovnp{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_NP, EFLAGS))]>, TB;
|
|
def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovo{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_O, EFLAGS))]>, TB;
|
|
def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"cmovno{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
|
|
X86_COND_NO, EFLAGS))]>, TB;
|
|
} // isCommutable = 1
|
|
|
|
def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovb{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_B, EFLAGS))]>, TB;
|
|
def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovae{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_AE, EFLAGS))]>, TB;
|
|
def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmove{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_E, EFLAGS))]>, TB;
|
|
def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovne{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_NE, EFLAGS))]>, TB;
|
|
def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovbe{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_BE, EFLAGS))]>, TB;
|
|
def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmova{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_A, EFLAGS))]>, TB;
|
|
def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovl{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_L, EFLAGS))]>, TB;
|
|
def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovge{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_GE, EFLAGS))]>, TB;
|
|
def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovle{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_LE, EFLAGS))]>, TB;
|
|
def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovg{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_G, EFLAGS))]>, TB;
|
|
def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovs{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_S, EFLAGS))]>, TB;
|
|
def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovns{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_NS, EFLAGS))]>, TB;
|
|
def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovp{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_P, EFLAGS))]>, TB;
|
|
def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovnp{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_NP, EFLAGS))]>, TB;
|
|
def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovo{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_O, EFLAGS))]>, TB;
|
|
def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
|
|
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
|
"cmovno{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
|
|
X86_COND_NO, EFLAGS))]>, TB;
|
|
} // isTwoAddress
|
|
|
|
// Use sbb to materialize carry flag into a GPR.
|
|
let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
|
|
def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins),
|
|
"sbb{q}\t$dst, $dst",
|
|
[(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
|
|
|
|
def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
|
|
(SETB_C64r)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Conversion Instructions...
|
|
//
|
|
|
|
// f64 -> signed i64
|
|
def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
|
|
"cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
|
|
"cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
|
|
def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
|
|
"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse2_cvtsd2si64 VR128:$src))]>;
|
|
def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
|
|
(ins f128mem:$src),
|
|
"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (int_x86_sse2_cvtsd2si64
|
|
(load addr:$src)))]>;
|
|
def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
|
|
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (fp_to_sint FR64:$src))]>;
|
|
def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
|
|
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
|
|
def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
|
|
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse2_cvttsd2si64 VR128:$src))]>;
|
|
def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
|
|
(ins f128mem:$src),
|
|
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse2_cvttsd2si64
|
|
(load addr:$src)))]>;
|
|
|
|
// Signed i64 -> f64
|
|
def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
|
|
"cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (sint_to_fp GR64:$src))]>;
|
|
def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
|
|
"cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
|
|
"cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(int_x86_sse2_cvtsi642sd VR128:$src1,
|
|
GR64:$src2))]>;
|
|
def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
|
|
"cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(int_x86_sse2_cvtsi642sd VR128:$src1,
|
|
(loadi64 addr:$src2)))]>;
|
|
} // isTwoAddress
|
|
|
|
// Signed i64 -> f32
|
|
def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
|
|
"cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (sint_to_fp GR64:$src))]>;
|
|
def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
|
|
"cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
|
|
|
|
let isTwoAddress = 1 in {
|
|
def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
|
|
"cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(int_x86_sse_cvtsi642ss VR128:$src1,
|
|
GR64:$src2))]>;
|
|
def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, i64mem:$src2),
|
|
"cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(int_x86_sse_cvtsi642ss VR128:$src1,
|
|
(loadi64 addr:$src2)))]>;
|
|
}
|
|
|
|
// f32 -> signed i64
|
|
def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
|
|
"cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
|
|
"cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
|
|
def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
|
|
"cvtss2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse_cvtss2si64 VR128:$src))]>;
|
|
def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
|
|
"cvtss2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (int_x86_sse_cvtss2si64
|
|
(load addr:$src)))]>;
|
|
def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
|
|
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (fp_to_sint FR32:$src))]>;
|
|
def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
|
|
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
|
|
def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
|
|
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse_cvttss2si64 VR128:$src))]>;
|
|
def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
|
|
(ins f32mem:$src),
|
|
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse_cvttss2si64 (load addr:$src)))]>;
|
|
|
|
// Descriptor-table support instructions
|
|
|
|
// LLDT is not interpreted specially in 64-bit mode because there is no sign
|
|
// extension.
|
|
def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
|
|
"sldt{q}\t$dst", []>, TB;
|
|
def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
|
"sldt{q}\t$dst", []>, TB;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Alias Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
|
|
// equivalent due to implicit zero-extending, and it sometimes has a smaller
|
|
// encoding.
|
|
// FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
|
|
// when we have a better way to specify isel priority.
|
|
let AddedComplexity = 1 in
|
|
def : Pat<(i64 0),
|
|
(SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
|
|
|
|
|
|
// Materialize i64 constant where top 32-bits are zero.
|
|
let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
|
def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
|
|
"", [(set GR64:$dst, i64immZExt32:$src)]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Thread Local Storage Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// All calls clobber the non-callee saved registers. RSP is marked as
|
|
// a use to prevent stack-pointer assignments that appear immediately
|
|
// before calls from potentially appearing dead.
|
|
let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
|
|
FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
|
|
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
|
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
|
|
Uses = [RSP] in
|
|
def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
|
|
".byte\t0x66; "
|
|
"leaq\t$sym(%rip), %rdi; "
|
|
".word\t0x6666; "
|
|
"rex64; "
|
|
"call\t__tls_get_addr@PLT",
|
|
[(X86tlsaddr tls64addr:$sym)]>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
let AddedComplexity = 5, isCodeGenOnly = 1 in
|
|
def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
"movq\t%gs:$src, $dst",
|
|
[(set GR64:$dst, (gsload addr:$src))]>, SegGS;
|
|
|
|
let AddedComplexity = 5, isCodeGenOnly = 1 in
|
|
def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
"movq\t%fs:$src, $dst",
|
|
[(set GR64:$dst, (fsload addr:$src))]>, SegFS;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Atomic Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Defs = [RAX, EFLAGS], Uses = [RAX] in {
|
|
def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
|
|
"lock\n\t"
|
|
"cmpxchgq\t$swap,$ptr",
|
|
[(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
|
|
}
|
|
|
|
let Constraints = "$val = $dst" in {
|
|
let Defs = [EFLAGS] in
|
|
def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
|
|
"lock\n\t"
|
|
"xadd\t$val, $ptr",
|
|
[(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
|
|
TB, LOCK;
|
|
|
|
def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
|
|
(ins GR64:$val,i64mem:$ptr),
|
|
"xchg{q}\t{$val, $ptr|$ptr, $val}",
|
|
[(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
|
|
|
|
def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
|
|
"xchg{q}\t{$val, $src|$src, $val}", []>;
|
|
}
|
|
|
|
def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
|
"xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
"xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
|
"cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
"cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
|
|
"cmpxchg16b\t$dst", []>, TB;
|
|
|
|
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
|
|
"xchg{q}\t{$src, %rax|%rax, $src}", []>;
|
|
|
|
// Optimized codegen when the non-memory output is not used.
|
|
let Defs = [EFLAGS] in {
|
|
// FIXME: Use normal add / sub instructions and add lock prefix dynamically.
|
|
def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
|
"lock\n\t"
|
|
"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|
def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
|
|
(ins i64mem:$dst, i64i8imm :$src2),
|
|
"lock\n\t"
|
|
"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|
def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
|
|
(ins i64mem:$dst, i64i32imm :$src2),
|
|
"lock\n\t"
|
|
"add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|
def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
|
"lock\n\t"
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|
def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
|
|
(ins i64mem:$dst, i64i8imm :$src2),
|
|
"lock\n\t"
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|
def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
|
|
(ins i64mem:$dst, i64i32imm:$src2),
|
|
"lock\n\t"
|
|
"sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|
def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
|
|
"lock\n\t"
|
|
"inc{q}\t$dst", []>, LOCK;
|
|
def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
|
|
"lock\n\t"
|
|
"dec{q}\t$dst", []>, LOCK;
|
|
}
|
|
// Atomic exchange, and, or, xor
|
|
let Constraints = "$val = $dst", Defs = [EFLAGS],
|
|
usesCustomInserter = 1 in {
|
|
def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
|
"#ATOMAND64 PSEUDO!",
|
|
[(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
|
|
def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
|
"#ATOMOR64 PSEUDO!",
|
|
[(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
|
|
def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
|
"#ATOMXOR64 PSEUDO!",
|
|
[(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
|
|
def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
|
"#ATOMNAND64 PSEUDO!",
|
|
[(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
|
|
def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
|
|
"#ATOMMIN64 PSEUDO!",
|
|
[(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
|
|
def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
|
"#ATOMMAX64 PSEUDO!",
|
|
[(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
|
|
def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
|
"#ATOMUMIN64 PSEUDO!",
|
|
[(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
|
|
def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
|
|
"#ATOMUMAX64 PSEUDO!",
|
|
[(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
|
|
}
|
|
|
|
// Segmentation support instructions
|
|
|
|
// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
|
|
def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
|
|
"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
|
|
"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|
"lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|
"lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
def SWPGS : I<0x01, RawFrm, (outs), (ins), "swpgs", []>, TB;
|
|
|
|
def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
|
|
"push{q}\t%fs", []>, TB;
|
|
def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
|
|
"push{q}\t%gs", []>, TB;
|
|
|
|
def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
|
|
"pop{q}\t%fs", []>, TB;
|
|
def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
|
|
"pop{q}\t%gs", []>, TB;
|
|
|
|
def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
|
"lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
|
"lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
|
"lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
// Specialized register support
|
|
|
|
// no m form encodable; use SMSW16m
|
|
def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
|
|
"smsw{q}\t$dst", []>, TB;
|
|
|
|
// String manipulation instructions
|
|
|
|
def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
|
|
// code model mode, should use 'movabs'. FIXME: This is really a hack, the
|
|
// 'movabs' predicate should handle this sort of thing.
|
|
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
|
|
(MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
|
|
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
|
|
(MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
|
|
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
|
|
(MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
|
|
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
|
|
(MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
|
|
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
|
|
(MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
|
|
|
|
// In static codegen with small code model, we can get the address of a label
|
|
// into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
|
|
// the MOV64ri64i32 should accept these.
|
|
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
|
|
(MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
|
|
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
|
|
(MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
|
|
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
|
|
(MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
|
|
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
|
|
(MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
|
|
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
|
|
(MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
|
|
|
|
// In kernel code model, we can get the address of a label
|
|
// into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
|
|
// the MOV64ri32 should accept these.
|
|
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
|
|
(MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
|
|
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
|
|
(MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
|
|
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
|
|
(MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
|
|
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
|
|
(MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
|
|
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
|
|
(MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
|
|
|
|
// If we have small model and -static mode, it is safe to store global addresses
|
|
// directly as immediates. FIXME: This is really a hack, the 'imm' predicate
|
|
// for MOV64mi32 should handle this sort of thing.
|
|
def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
|
|
(MOV64mi32 addr:$dst, tconstpool:$src)>,
|
|
Requires<[NearData, IsStatic]>;
|
|
def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
|
|
(MOV64mi32 addr:$dst, tjumptable:$src)>,
|
|
Requires<[NearData, IsStatic]>;
|
|
def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
|
|
(MOV64mi32 addr:$dst, tglobaladdr:$src)>,
|
|
Requires<[NearData, IsStatic]>;
|
|
def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
|
|
(MOV64mi32 addr:$dst, texternalsym:$src)>,
|
|
Requires<[NearData, IsStatic]>;
|
|
def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
|
|
(MOV64mi32 addr:$dst, tblockaddress:$src)>,
|
|
Requires<[NearData, IsStatic]>;
|
|
|
|
// Calls
|
|
// Direct PC relative function call for small code model. 32-bit displacement
|
|
// sign extended to 64-bit.
|
|
def : Pat<(X86call (i64 tglobaladdr:$dst)),
|
|
(CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
|
|
def : Pat<(X86call (i64 texternalsym:$dst)),
|
|
(CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
|
|
|
|
def : Pat<(X86call (i64 tglobaladdr:$dst)),
|
|
(WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
|
|
def : Pat<(X86call (i64 texternalsym:$dst)),
|
|
(WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
|
|
|
|
// tailcall stuff
|
|
def : Pat<(X86tcret GR64:$dst, imm:$off),
|
|
(TCRETURNri64 GR64:$dst, imm:$off)>;
|
|
|
|
def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
|
|
(TCRETURNdi64 tglobaladdr:$dst, imm:$off)>;
|
|
|
|
def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
|
|
(TCRETURNdi64 texternalsym:$dst, imm:$off)>;
|
|
|
|
// Comparisons.
|
|
|
|
// TEST R,R is smaller than CMP R,0
|
|
def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
|
|
(TEST64rr GR64:$src1, GR64:$src1)>;
|
|
|
|
// Conditional moves with folded loads with operands swapped and conditions
|
|
// inverted.
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
|
|
(CMOVAE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
|
|
(CMOVB64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
|
|
(CMOVNE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
|
|
(CMOVE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
|
|
(CMOVA64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
|
|
(CMOVBE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
|
|
(CMOVGE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
|
|
(CMOVL64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
|
|
(CMOVG64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
|
|
(CMOVLE64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
|
|
(CMOVNP64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
|
|
(CMOVP64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
|
|
(CMOVNS64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
|
|
(CMOVS64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
|
|
(CMOVNO64rm GR64:$src2, addr:$src1)>;
|
|
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
|
|
(CMOVO64rm GR64:$src2, addr:$src1)>;
|
|
|
|
// zextload bool -> zextload byte
|
|
def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
|
|
|
|
// extload
|
|
// When extloading from 16-bit and smaller memory locations into 64-bit
|
|
// registers, use zero-extending loads so that the entire 64-bit register is
|
|
// defined, avoiding partial-register updates.
|
|
def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
|
|
def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
|
|
def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
|
|
// For other extloads, use subregs, since the high contents of the register are
|
|
// defined after an extload.
|
|
def : Pat<(extloadi64i32 addr:$src),
|
|
(SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
|
|
x86_subreg_32bit)>;
|
|
|
|
// anyext. Define these to do an explicit zero-extend to
|
|
// avoid partial-register updates.
|
|
def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
|
|
def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
|
|
def : Pat<(i64 (anyext GR32:$src)),
|
|
(SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Some peepholes
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Odd encoding trick: -128 fits into an 8-bit immediate field while
|
|
// +128 doesn't, so in this special case use a sub instead of an add.
|
|
def : Pat<(add GR64:$src1, 128),
|
|
(SUB64ri8 GR64:$src1, -128)>;
|
|
def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
|
|
(SUB64mi8 addr:$dst, -128)>;
|
|
|
|
// The same trick applies for 32-bit immediate fields in 64-bit
|
|
// instructions.
|
|
def : Pat<(add GR64:$src1, 0x0000000080000000),
|
|
(SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
|
|
def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
|
|
(SUB64mi32 addr:$dst, 0xffffffff80000000)>;
|
|
|
|
// r & (2^32-1) ==> movz
|
|
def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
|
|
(MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
|
|
// r & (2^16-1) ==> movz
|
|
def : Pat<(and GR64:$src, 0xffff),
|
|
(MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
|
|
// r & (2^8-1) ==> movz
|
|
def : Pat<(and GR64:$src, 0xff),
|
|
(MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
|
|
// r & (2^8-1) ==> movz
|
|
def : Pat<(and GR32:$src1, 0xff),
|
|
(MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
|
|
Requires<[In64BitMode]>;
|
|
// r & (2^8-1) ==> movz
|
|
def : Pat<(and GR16:$src1, 0xff),
|
|
(MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
// sext_inreg patterns
|
|
def : Pat<(sext_inreg GR64:$src, i32),
|
|
(MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
|
|
def : Pat<(sext_inreg GR64:$src, i16),
|
|
(MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
|
|
def : Pat<(sext_inreg GR64:$src, i8),
|
|
(MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
|
|
def : Pat<(sext_inreg GR32:$src, i8),
|
|
(MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(sext_inreg GR16:$src, i8),
|
|
(MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
// trunc patterns
|
|
def : Pat<(i32 (trunc GR64:$src)),
|
|
(EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
|
|
def : Pat<(i16 (trunc GR64:$src)),
|
|
(EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
|
|
def : Pat<(i8 (trunc GR64:$src)),
|
|
(EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
|
|
def : Pat<(i8 (trunc GR32:$src)),
|
|
(EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(i8 (trunc GR16:$src)),
|
|
(EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
// h-register tricks.
|
|
// For now, be conservative on x86-64 and use an h-register extract only if the
|
|
// value is immediately zero-extended or stored, which are somewhat common
|
|
// cases. This uses a bunch of code to prevent a register requiring a REX prefix
|
|
// from being allocated in the same instruction as the h register, as there's
|
|
// currently no way to describe this requirement to the register allocator.
|
|
|
|
// h-register extract and zero-extend.
|
|
def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
|
|
(SUBREG_TO_REG
|
|
(i64 0),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
|
|
x86_subreg_8bit_hi)),
|
|
x86_subreg_32bit)>;
|
|
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
|
|
x86_subreg_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(srl_su GR16:$src, (i8 8)),
|
|
(EXTRACT_SUBREG
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
x86_subreg_8bit_hi)),
|
|
x86_subreg_16bit)>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
x86_subreg_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
x86_subreg_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
|
|
(SUBREG_TO_REG
|
|
(i64 0),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
x86_subreg_8bit_hi)),
|
|
x86_subreg_32bit)>;
|
|
def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
|
|
(SUBREG_TO_REG
|
|
(i64 0),
|
|
(MOVZX32_NOREXrr8
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
x86_subreg_8bit_hi)),
|
|
x86_subreg_32bit)>;
|
|
|
|
// h-register extract and store.
|
|
def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
|
|
(MOV8mr_NOREX
|
|
addr:$dst,
|
|
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
|
|
x86_subreg_8bit_hi))>;
|
|
def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
|
|
(MOV8mr_NOREX
|
|
addr:$dst,
|
|
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
|
|
x86_subreg_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
|
|
(MOV8mr_NOREX
|
|
addr:$dst,
|
|
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|
x86_subreg_8bit_hi))>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
// (shl x, 1) ==> (add x, x)
|
|
def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
|
|
|
|
// (shl x (and y, 63)) ==> (shl x, y)
|
|
def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
|
|
(SHL64rCL GR64:$src1)>;
|
|
def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
|
|
(SHL64mCL addr:$dst)>;
|
|
|
|
def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
|
|
(SHR64rCL GR64:$src1)>;
|
|
def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
|
|
(SHR64mCL addr:$dst)>;
|
|
|
|
def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
|
|
(SAR64rCL GR64:$src1)>;
|
|
def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
|
|
(SAR64mCL addr:$dst)>;
|
|
|
|
// (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
|
|
def : Pat<(or (srl GR64:$src1, CL:$amt),
|
|
(shl GR64:$src2, (sub 64, CL:$amt))),
|
|
(SHRD64rrCL GR64:$src1, GR64:$src2)>;
|
|
|
|
def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
|
|
(shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
|
|
(SHRD64mrCL addr:$dst, GR64:$src2)>;
|
|
|
|
def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
|
|
(shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
|
|
(SHRD64rrCL GR64:$src1, GR64:$src2)>;
|
|
|
|
def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
|
|
(shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
|
|
addr:$dst),
|
|
(SHRD64mrCL addr:$dst, GR64:$src2)>;
|
|
|
|
def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
|
|
(SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
|
|
|
|
def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
|
|
GR64:$src2, (i8 imm:$amt2)), addr:$dst),
|
|
(SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
|
|
|
|
// (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
|
|
def : Pat<(or (shl GR64:$src1, CL:$amt),
|
|
(srl GR64:$src2, (sub 64, CL:$amt))),
|
|
(SHLD64rrCL GR64:$src1, GR64:$src2)>;
|
|
|
|
def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
|
|
(srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
|
|
(SHLD64mrCL addr:$dst, GR64:$src2)>;
|
|
|
|
def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
|
|
(srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
|
|
(SHLD64rrCL GR64:$src1, GR64:$src2)>;
|
|
|
|
def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
|
|
(srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
|
|
addr:$dst),
|
|
(SHLD64mrCL addr:$dst, GR64:$src2)>;
|
|
|
|
def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
|
|
(SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
|
|
|
|
def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
|
|
GR64:$src2, (i8 imm:$amt2)), addr:$dst),
|
|
(SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
|
|
|
|
// X86 specific add which produces a flag.
|
|
def : Pat<(addc GR64:$src1, GR64:$src2),
|
|
(ADD64rr GR64:$src1, GR64:$src2)>;
|
|
def : Pat<(addc GR64:$src1, (load addr:$src2)),
|
|
(ADD64rm GR64:$src1, addr:$src2)>;
|
|
def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
|
|
(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
|
|
(ADD64ri32 GR64:$src1, imm:$src2)>;
|
|
|
|
def : Pat<(subc GR64:$src1, GR64:$src2),
|
|
(SUB64rr GR64:$src1, GR64:$src2)>;
|
|
def : Pat<(subc GR64:$src1, (load addr:$src2)),
|
|
(SUB64rm GR64:$src1, addr:$src2)>;
|
|
def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
|
|
(SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(subc GR64:$src1, imm:$src2),
|
|
(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// EFLAGS-defining Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Register-Register Addition with EFLAGS result
|
|
def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
|
|
(implicit EFLAGS)),
|
|
(ADD64rr GR64:$src1, GR64:$src2)>;
|
|
|
|
// Register-Integer Addition with EFLAGS result
|
|
def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
|
|
(implicit EFLAGS)),
|
|
(ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
|
|
(implicit EFLAGS)),
|
|
(ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Register-Memory Addition with EFLAGS result
|
|
def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
|
|
(implicit EFLAGS)),
|
|
(ADD64rm GR64:$src1, addr:$src2)>;
|
|
|
|
// Memory-Register Addition with EFLAGS result
|
|
def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(ADD64mr addr:$dst, GR64:$src2)>;
|
|
def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
|
|
i64immSExt32:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
|
|
|
|
// Register-Register Subtraction with EFLAGS result
|
|
def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
|
|
(implicit EFLAGS)),
|
|
(SUB64rr GR64:$src1, GR64:$src2)>;
|
|
|
|
// Register-Memory Subtraction with EFLAGS result
|
|
def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
|
|
(implicit EFLAGS)),
|
|
(SUB64rm GR64:$src1, addr:$src2)>;
|
|
|
|
// Register-Integer Subtraction with EFLAGS result
|
|
def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
|
|
(implicit EFLAGS)),
|
|
(SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
|
|
(implicit EFLAGS)),
|
|
(SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Memory-Register Subtraction with EFLAGS result
|
|
def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(SUB64mr addr:$dst, GR64:$src2)>;
|
|
|
|
// Memory-Integer Subtraction with EFLAGS result
|
|
def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
|
|
i64immSExt8:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
|
|
i64immSExt32:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
|
|
|
|
// Register-Register Signed Integer Multiplication with EFLAGS result
|
|
def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
|
|
(implicit EFLAGS)),
|
|
(IMUL64rr GR64:$src1, GR64:$src2)>;
|
|
|
|
// Register-Memory Signed Integer Multiplication with EFLAGS result
|
|
def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
|
|
(implicit EFLAGS)),
|
|
(IMUL64rm GR64:$src1, addr:$src2)>;
|
|
|
|
// Register-Integer Signed Integer Multiplication with EFLAGS result
|
|
def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
|
|
(implicit EFLAGS)),
|
|
(IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
|
|
(implicit EFLAGS)),
|
|
(IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Memory-Integer Signed Integer Multiplication with EFLAGS result
|
|
def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
|
|
(implicit EFLAGS)),
|
|
(IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
|
|
(implicit EFLAGS)),
|
|
(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
|
|
|
|
// INC and DEC with EFLAGS result. Note that these do not set CF.
|
|
def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
|
|
(INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
|
|
def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
|
|
def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
|
|
(DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
|
|
def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
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|
|
|
def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
|
|
(INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
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|
def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
|
|
def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
|
|
(DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
|
|
def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
|
|
|
|
def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
|
|
(INC64r GR64:$src)>;
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|
def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(INC64m addr:$dst)>;
|
|
def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
|
|
(DEC64r GR64:$src)>;
|
|
def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(DEC64m addr:$dst)>;
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|
|
|
// Register-Register Logical Or with EFLAGS result
|
|
def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
|
|
(implicit EFLAGS)),
|
|
(OR64rr GR64:$src1, GR64:$src2)>;
|
|
|
|
// Register-Integer Logical Or with EFLAGS result
|
|
def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
|
|
(implicit EFLAGS)),
|
|
(OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
|
|
(implicit EFLAGS)),
|
|
(OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Register-Memory Logical Or with EFLAGS result
|
|
def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
|
|
(implicit EFLAGS)),
|
|
(OR64rm GR64:$src1, addr:$src2)>;
|
|
|
|
// Memory-Register Logical Or with EFLAGS result
|
|
def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(OR64mr addr:$dst, GR64:$src2)>;
|
|
def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(OR64mi8 addr:$dst, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(OR64mi32 addr:$dst, i64immSExt32:$src2)>;
|
|
|
|
// Register-Register Logical XOr with EFLAGS result
|
|
def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
|
|
(implicit EFLAGS)),
|
|
(XOR64rr GR64:$src1, GR64:$src2)>;
|
|
|
|
// Register-Integer Logical XOr with EFLAGS result
|
|
def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
|
|
(implicit EFLAGS)),
|
|
(XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
|
|
(implicit EFLAGS)),
|
|
(XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Register-Memory Logical XOr with EFLAGS result
|
|
def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
|
|
(implicit EFLAGS)),
|
|
(XOR64rm GR64:$src1, addr:$src2)>;
|
|
|
|
// Memory-Register Logical XOr with EFLAGS result
|
|
def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(XOR64mr addr:$dst, GR64:$src2)>;
|
|
def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
|
|
i64immSExt32:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
|
|
|
|
// Register-Register Logical And with EFLAGS result
|
|
def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
|
|
(implicit EFLAGS)),
|
|
(AND64rr GR64:$src1, GR64:$src2)>;
|
|
|
|
// Register-Integer Logical And with EFLAGS result
|
|
def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
|
|
(implicit EFLAGS)),
|
|
(AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
|
|
(implicit EFLAGS)),
|
|
(AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
|
|
|
// Register-Memory Logical And with EFLAGS result
|
|
def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
|
|
(implicit EFLAGS)),
|
|
(AND64rm GR64:$src1, addr:$src2)>;
|
|
|
|
// Memory-Register Logical And with EFLAGS result
|
|
def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(AND64mr addr:$dst, GR64:$src2)>;
|
|
def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(AND64mi8 addr:$dst, i64immSExt8:$src2)>;
|
|
def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
|
|
i64immSExt32:$src2),
|
|
addr:$dst),
|
|
(implicit EFLAGS)),
|
|
(AND64mi32 addr:$dst, i64immSExt32:$src2)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86-64 SSE Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Move instructions...
|
|
|
|
def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
|
|
"mov{d|q}\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,
|
|
(v2i64 (scalar_to_vector GR64:$src)))]>;
|
|
def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
|
|
"mov{d|q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
|
|
(iPTR 0)))]>;
|
|
|
|
def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
|
|
"mov{d|q}\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (bitconvert GR64:$src))]>;
|
|
def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
|
|
"movq\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
|
|
|
|
def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
|
|
"mov{d|q}\t{$src, $dst|$dst, $src}",
|
|
[(set GR64:$dst, (bitconvert FR64:$src))]>;
|
|
def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
|
|
"movq\t{$src, $dst|$dst, $src}",
|
|
[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86-64 SSE4.1 Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
|
|
multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
|
|
def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
|
|
(ins VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set GR64:$dst,
|
|
(extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
|
|
def mr : SS4AIi8<opc, MRMDestMem, (outs),
|
|
(ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(store (extractelt (v2i64 VR128:$src1), imm:$src2),
|
|
addr:$dst)]>, OpSize, REX_W;
|
|
}
|
|
|
|
defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
|
|
|
|
let isTwoAddress = 1 in {
|
|
multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
|
|
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
|
|
OpSize, REX_W;
|
|
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
|
|
imm:$src3)))]>, OpSize, REX_W;
|
|
}
|
|
}
|
|
|
|
defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
|
|
|
|
// -disable-16bit support.
|
|
def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
|
|
(MOV16mi addr:$dst, imm:$src)>;
|
|
def : Pat<(truncstorei16 GR64:$src, addr:$dst),
|
|
(MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
|
|
def : Pat<(i64 (sextloadi16 addr:$dst)),
|
|
(MOVSX64rm16 addr:$dst)>;
|
|
def : Pat<(i64 (zextloadi16 addr:$dst)),
|
|
(MOVZX64rm16 addr:$dst)>;
|
|
def : Pat<(i64 (extloadi16 addr:$dst)),
|
|
(MOVZX64rm16 addr:$dst)>;
|