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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
2.6 KiB
LLVM
90 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; Check the GHC call convention works (aarch64)
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@base = external global i64 ; assigned to register: r19
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@sp = external global i64 ; assigned to register: r20
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@hp = external global i64 ; assigned to register: r21
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@r1 = external global i64 ; assigned to register: r22
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@r2 = external global i64 ; assigned to register: r23
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@r3 = external global i64 ; assigned to register: r24
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@r4 = external global i64 ; assigned to register: r25
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@r5 = external global i64 ; assigned to register: r26
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@r6 = external global i64 ; assigned to register: r27
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@splim = external global i64 ; assigned to register: r28
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@f1 = external global float ; assigned to register: s8
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@f2 = external global float ; assigned to register: s9
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@f3 = external global float ; assigned to register: s10
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@f4 = external global float ; assigned to register: s11
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@d1 = external global double ; assigned to register: d12
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@d2 = external global double ; assigned to register: d13
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@d3 = external global double ; assigned to register: d14
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@d4 = external global double ; assigned to register: d15
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define ghccc i64 @addtwo(i64 %x, i64 %y) nounwind {
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entry:
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; CHECK-LABEL: addtwo
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; CHECK: add x0, x19, x20
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; CHECK-NEXT: ret
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%0 = add i64 %x, %y
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ret i64 %0
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}
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define void @zap(i64 %a, i64 %b) nounwind {
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entry:
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; CHECK-LABEL: zap
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; CHECK-NOT: mov {{x[0-9]+}}, sp
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; CHECK: bl addtwo
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; CHECK-NEXT: bl foo
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%0 = call ghccc i64 @addtwo(i64 %a, i64 %b)
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call void @foo() nounwind
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ret void
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}
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define ghccc void @foo_i64 () nounwind {
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entry:
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; CHECK-LABEL: foo_i64
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; CHECK: adrp {{x[0-9]+}}, base
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; CHECK-NEXT: ldr x19, [{{x[0-9]+}}, :lo12:base]
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; CHECK-NEXT: bl bar_i64
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; CHECK-NEXT: ret
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%0 = load i64, i64* @base
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tail call ghccc void @bar_i64( i64 %0 ) nounwind
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ret void
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}
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define ghccc void @foo_float () nounwind {
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entry:
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; CHECK-LABEL: foo_float
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; CHECK: adrp {{x[0-9]+}}, f1
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; CHECK-NEXT: ldr s8, [{{x[0-9]+}}, :lo12:f1]
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; CHECK-NEXT: bl bar_float
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; CHECK-NEXT: ret
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%0 = load float, float* @f1
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tail call ghccc void @bar_float( float %0 ) nounwind
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ret void
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}
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define ghccc void @foo_double () nounwind {
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entry:
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; CHECK-LABEL: foo_double
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; CHECK: adrp {{x[0-9]+}}, d1
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; CHECK-NEXT: ldr d12, [{{x[0-9]+}}, :lo12:d1]
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; CHECK-NEXT: bl bar_double
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; CHECK-NEXT: ret
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%0 = load double, double* @d1
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tail call ghccc void @bar_double( double %0 ) nounwind
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ret void
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}
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declare ghccc void @foo ()
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declare ghccc void @bar_i64 (i64)
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declare ghccc void @bar_float (float)
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declare ghccc void @bar_double (double)
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