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d36f5af224
A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
2.4 KiB
LLVM
44 lines
2.4 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -verify-coalescing
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; PR11841
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7-none-linux-eabi"
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; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
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define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
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bb:
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%tmp = load <2 x float>* undef, align 8, !tbaa !0
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%tmp2 = extractelement <2 x float> %tmp, i32 0
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%tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
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%tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
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%tmp5 = insertelement <4 x float> %tmp4, float 0.000000e+00, i32 2
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%tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 3
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%tmp7 = extractelement <2 x float> %tmp, i32 1
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%tmp8 = insertelement <4 x float> %tmp3, float %tmp7, i32 1
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%tmp9 = insertelement <4 x float> %tmp8, float 0.000000e+00, i32 2
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%tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 3
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%tmp11 = bitcast <4 x float> %tmp6 to <2 x i64>
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%tmp12 = shufflevector <2 x i64> %tmp11, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp13 = bitcast <1 x i64> %tmp12 to <2 x float>
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%tmp14 = shufflevector <2 x float> %tmp13, <2 x float> undef, <4 x i32> zeroinitializer
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%tmp15 = bitcast <4 x float> %tmp14 to <2 x i64>
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%tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp17 = bitcast <1 x i64> %tmp16 to <2 x float>
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%tmp18 = extractelement <2 x float> %tmp17, i32 0
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tail call arm_aapcs_vfpcc void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind
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%tmp19 = bitcast <4 x float> %tmp10 to <2 x i64>
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%tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp21 = bitcast <1 x i64> %tmp20 to <2 x float>
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%tmp22 = shufflevector <2 x float> %tmp21, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%tmp23 = bitcast <4 x float> %tmp22 to <2 x i64>
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%tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitializer
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%tmp25 = bitcast <1 x i64> %tmp24 to <2 x float>
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%tmp26 = extractelement <2 x float> %tmp25, i32 0
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tail call arm_aapcs_vfpcc void @bar(i8* undef, float undef, float %tmp26, float 0.000000e+00) nounwind
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ret void
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}
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declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
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!0 = metadata !{metadata !"omnipotent char", metadata !1}
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!1 = metadata !{metadata !"Simple C/C++ TBAA", null}
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