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This fixes PEI as previously described, but correctly handles the case where the instruction defining the virtual register to be scavenged is the first in the block. Arnold provided me with a bugpoint-reduced test case, but even that seems too large to use as a regression test. If I'm successful in cleaning it up then I'll commit that as well. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178919 91177308-0d34-0410-b5e6-96231b3b80d8
443 lines
14 KiB
C++
443 lines
14 KiB
C++
//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the machine register scavenger. It can provide
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// information, such as unused registers, at any point in a machine basic block.
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// It also provides a mechanism to make registers available by evicting them to
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// spill slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reg-scavenging"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg) {
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RegsAvailable.reset(Reg);
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for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
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RegsAvailable.reset(*SubRegs);
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}
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bool RegScavenger::isAliasUsed(unsigned Reg) const {
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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if (isUsed(*AI, *AI == Reg))
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return true;
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return false;
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}
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void RegScavenger::initRegState() {
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for (SmallVector<ScavengedInfo, 2>::iterator I = Scavenged.begin(),
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IE = Scavenged.end(); I != IE; ++I) {
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I->Reg = 0;
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I->Restore = NULL;
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}
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// All registers started out unused.
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RegsAvailable.set();
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if (!MBB)
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return;
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// Live-in registers are in use.
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for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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setUsed(*I);
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// Pristine CSRs are also unavailable.
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BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
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for (int I = PR.find_first(); I>0; I = PR.find_next(I))
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setUsed(I);
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}
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void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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MachineFunction &MF = *mbb->getParent();
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const TargetMachine &TM = MF.getTarget();
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TII = TM.getInstrInfo();
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TRI = TM.getRegisterInfo();
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MRI = &MF.getRegInfo();
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assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
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"Target changed?");
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// It is not possible to use the register scavenger after late optimization
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// passes that don't preserve accurate liveness information.
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assert(MRI->tracksLiveness() &&
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"Cannot use register scavenger with inaccurate liveness");
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// Self-initialize.
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if (!MBB) {
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NumPhysRegs = TRI->getNumRegs();
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RegsAvailable.resize(NumPhysRegs);
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KillRegs.resize(NumPhysRegs);
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DefRegs.resize(NumPhysRegs);
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// Create callee-saved registers bitvector.
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CalleeSavedRegs.resize(NumPhysRegs);
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const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF);
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if (CSRegs != NULL)
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for (unsigned i = 0; CSRegs[i]; ++i)
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CalleeSavedRegs.set(CSRegs[i]);
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}
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MBB = mbb;
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initRegState();
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Tracking = false;
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}
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void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
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BV.set(Reg);
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for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
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BV.set(*SubRegs);
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}
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void RegScavenger::determineKillsAndDefs() {
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assert(Tracking && "Must be tracking to determine kills and defs");
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MachineInstr *MI = MBBI;
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assert(!MI->isDebugValue() && "Debug values have no kills or defs");
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// Find out which registers are early clobbered, killed, defined, and marked
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// def-dead in this instruction.
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// FIXME: The scavenger is not predication aware. If the instruction is
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// predicated, conservatively assume "kill" markers do not actually kill the
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// register. Similarly ignores "dead" markers.
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bool isPred = TII->isPredicated(MI);
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KillRegs.reset();
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DefRegs.reset();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegMask())
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(isPred ? DefRegs : KillRegs).setBitsNotInMask(MO.getRegMask());
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg))
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continue;
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if (MO.isUse()) {
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// Ignore undef uses.
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if (MO.isUndef())
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continue;
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if (!isPred && MO.isKill())
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addRegWithSubRegs(KillRegs, Reg);
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} else {
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assert(MO.isDef());
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if (!isPred && MO.isDead())
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addRegWithSubRegs(KillRegs, Reg);
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else
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addRegWithSubRegs(DefRegs, Reg);
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}
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}
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}
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void RegScavenger::unprocess() {
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assert(Tracking && "Cannot unprocess because we're not tracking");
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MachineInstr *MI = MBBI;
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if (!MI->isDebugValue()) {
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determineKillsAndDefs();
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// Commit the changes.
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setUsed(KillRegs);
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setUnused(DefRegs);
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}
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if (MBBI == MBB->begin()) {
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MBBI = MachineBasicBlock::iterator(NULL);
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Tracking = false;
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} else
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--MBBI;
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}
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void RegScavenger::forward() {
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// Move ptr forward.
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if (!Tracking) {
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MBBI = MBB->begin();
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Tracking = true;
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} else {
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assert(MBBI != MBB->end() && "Already past the end of the basic block!");
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MBBI = llvm::next(MBBI);
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}
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assert(MBBI != MBB->end() && "Already at the end of the basic block!");
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MachineInstr *MI = MBBI;
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for (SmallVector<ScavengedInfo, 2>::iterator I = Scavenged.begin(),
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IE = Scavenged.end(); I != IE; ++I) {
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if (I->Restore != MI)
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continue;
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I->Reg = 0;
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I->Restore = NULL;
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}
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if (MI->isDebugValue())
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return;
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determineKillsAndDefs();
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// Verify uses and defs.
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#ifndef NDEBUG
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) || isReserved(Reg))
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continue;
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if (MO.isUse()) {
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if (MO.isUndef())
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continue;
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if (!isUsed(Reg)) {
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// Check if it's partial live: e.g.
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// D0 = insert_subreg D0<undef>, S0
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// ... D0
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// The problem is the insert_subreg could be eliminated. The use of
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// D0 is using a partially undef value. This is not *incorrect* since
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// S1 is can be freely clobbered.
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// Ideally we would like a way to model this, but leaving the
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// insert_subreg around causes both correctness and performance issues.
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bool SubUsed = false;
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for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
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if (isUsed(*SubRegs)) {
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SubUsed = true;
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break;
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}
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if (!SubUsed) {
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MBB->getParent()->verify(NULL, "In Register Scavenger");
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llvm_unreachable("Using an undefined register!");
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}
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(void)SubUsed;
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}
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} else {
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assert(MO.isDef());
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#if 0
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// FIXME: Enable this once we've figured out how to correctly transfer
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// implicit kills during codegen passes like the coalescer.
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assert((KillRegs.test(Reg) || isUnused(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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#endif
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}
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}
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#endif // NDEBUG
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// Commit the changes.
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setUnused(KillRegs);
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setUsed(DefRegs);
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}
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void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
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used = RegsAvailable;
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used.flip();
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if (includeReserved)
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used |= MRI->getReservedRegs();
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else
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used.reset(MRI->getReservedRegs());
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
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I != E; ++I)
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if (!isAliasUsed(*I)) {
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DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) <<
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"\n");
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return *I;
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}
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return 0;
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}
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/// getRegsAvailable - Return all available registers in the register class
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/// in Mask.
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BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
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BitVector Mask(TRI->getNumRegs());
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
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I != E; ++I)
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if (!isAliasUsed(*I))
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Mask.set(*I);
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return Mask;
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}
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/// findSurvivorReg - Return the candidate register that is unused for the
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/// longest after StargMII. UseMI is set to the instruction where the search
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/// stopped.
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///
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/// No more than InstrLimit instructions are inspected.
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///
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unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
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BitVector &Candidates,
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unsigned InstrLimit,
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MachineBasicBlock::iterator &UseMI) {
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int Survivor = Candidates.find_first();
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assert(Survivor > 0 && "No candidates for scavenging");
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MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
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assert(StartMI != ME && "MI already at terminator");
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MachineBasicBlock::iterator RestorePointMI = StartMI;
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MachineBasicBlock::iterator MI = StartMI;
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bool inVirtLiveRange = false;
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for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
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if (MI->isDebugValue()) {
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++InstrLimit; // Don't count debug instructions
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continue;
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}
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bool isVirtKillInsn = false;
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bool isVirtDefInsn = false;
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// Remove any candidates touched by instruction.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegMask())
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Candidates.clearBitsNotInMask(MO.getRegMask());
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if (!MO.isReg() || MO.isUndef() || !MO.getReg())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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if (MO.isDef())
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isVirtDefInsn = true;
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else if (MO.isKill())
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isVirtKillInsn = true;
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continue;
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}
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for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
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Candidates.reset(*AI);
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}
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// If we're not in a virtual reg's live range, this is a valid
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// restore point.
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if (!inVirtLiveRange) RestorePointMI = MI;
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// Update whether we're in the live range of a virtual register
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if (isVirtKillInsn) inVirtLiveRange = false;
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if (isVirtDefInsn) inVirtLiveRange = true;
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// Was our survivor untouched by this instruction?
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if (Candidates.test(Survivor))
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continue;
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// All candidates gone?
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if (Candidates.none())
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break;
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Survivor = Candidates.find_first();
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}
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// If we ran off the end, that's where we want to restore.
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if (MI == ME) RestorePointMI = ME;
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assert (RestorePointMI != StartMI &&
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"No available scavenger restore location!");
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// We ran out of candidates, so stop the search.
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UseMI = RestorePointMI;
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return Survivor;
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}
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static unsigned getFrameIndexOperandNum(MachineInstr *MI) {
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unsigned i = 0;
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while (!MI->getOperand(i).isFI()) {
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++i;
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assert(i < MI->getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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return i;
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}
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unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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MachineBasicBlock::iterator I,
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int SPAdj) {
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// Consider all allocatable registers in the register class initially
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BitVector Candidates =
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TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
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// Exclude all the registers being used by the instruction.
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = I->getOperand(i);
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if (MO.isReg() && MO.getReg() != 0 &&
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!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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Candidates.reset(MO.getReg());
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}
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// Try to find a register that's unused if there is one, as then we won't
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// have to spill. Search explicitly rather than masking out based on
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// RegsAvailable, as RegsAvailable does not take aliases into account.
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// That's what getRegsAvailable() is for.
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BitVector Available = getRegsAvailable(RC);
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Available &= Candidates;
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if (Available.any())
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Candidates = Available;
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// Find the register whose use is furthest away.
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MachineBasicBlock::iterator UseMI;
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unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
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// If we found an unused register there is no reason to spill it.
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if (!isAliasUsed(SReg)) {
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DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
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return SReg;
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}
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// Find an available scavenging slot.
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unsigned SI;
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for (SI = 0; SI < Scavenged.size(); ++SI)
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if (Scavenged[SI].Reg == 0)
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break;
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if (SI == Scavenged.size()) {
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// We need to scavenge a register but have no spill slot, the target
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// must know how to do it (if not, we'll assert below).
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Scavenged.push_back(ScavengedInfo());
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}
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// Avoid infinite regress
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Scavenged[SI].Reg = SReg;
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// If the target knows how to save/restore the register, let it do so;
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// otherwise, use the emergency stack spill slot.
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if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
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// Spill the scavenged register before I.
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assert(Scavenged[SI].FrameIndex >= 0 &&
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"Cannot scavenge register without an emergency spill slot!");
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TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
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RC, TRI);
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MachineBasicBlock::iterator II = prior(I);
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unsigned FIOperandNum = getFrameIndexOperandNum(II);
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TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
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// Restore the scavenged register before its use (or first terminator).
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TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
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RC, TRI);
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II = prior(UseMI);
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FIOperandNum = getFrameIndexOperandNum(II);
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TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
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}
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Scavenged[SI].Restore = prior(UseMI);
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// Doing this here leads to infinite regress.
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// Scavenged[SI].Reg = SReg;
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DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
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"\n");
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return SReg;
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}
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