Owen Anderson 4a9f150926 When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore, ... CombinerAA cannot assume that different FrameIndex's never alias, but can instead use MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing. This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll when CombinerAA is enabled, modulo a different register allocation sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114348 91177308-0d34-0410-b5e6-96231b3b80d8		2010-09-20 20:39:59 +00:00
..
Alpha
ARM	Simplify ARM callee-saved register handling by removing the distinction	2010-09-20 19:32:20 +00:00
Blackfin
CBackend
CellSPU	Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.	2010-09-16 12:29:33 +00:00
CPP
Generic
MBlaze
Mips
MSP430
PIC16
PowerPC
PTX	Add the exit instruction to the PTX target.	2010-09-18 18:52:28 +00:00
SPARC
SystemZ
Thumb	Re-enable usage of the ARM base pointer. r113394 fixed the known failures.	2010-09-08 20:12:02 +00:00
Thumb2	Simplify ARM callee-saved register handling by removing the distinction	2010-09-20 19:32:20 +00:00
X86	When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore,	2010-09-20 20:39:59 +00:00
XCore