Chandler Carruth 4abb04a65c [x86] Revert r218588, r218589, and r218600. These patches were pursuing ... a flawed direction and causing miscompiles. Read on for details. Fundamentally, the premise of this patch series was to map VECTOR_SHUFFLE DAG nodes into VSELECT DAG nodes for all blends because we are going to *have* to lower to VSELECT nodes for some blends to trigger the instruction selection patterns of variable blend instructions. This doesn't actually work out so well. In order to match performance with the existing VECTOR_SHUFFLE lowering code, we would need to re-slice the blend in order to fit it into either the integer or floating point blends available on the ISA. When coming from VECTOR_SHUFFLE (or other vNi1 style VSELECT sources) this works well because the X86 backend ensures that these types of operands to VSELECT get sign extended into '-1' and '0' for true and false, allowing us to re-slice the bits in whatever granularity without changing semantics. However, if the VSELECT condition comes from some other source, for example code lowering vector comparisons, it will likely only have the required bit set -- the high bit. We can't blindly slice up this style of VSELECT. Reid found some code using Halide that triggers this and I'm hopeful to eventually get a test case, but I don't need it to understand why this is A Bad Idea. There is another aspect that makes this approach flawed. When in VECTOR_SHUFFLE form, we have very distilled information that represents the *constant* blend mask. Converting back to a VSELECT form actually can lose this information, and so I think now that it is better to treat this as VECTOR_SHUFFLE until the very last moment and only use VSELECT nodes for instruction selection purposes. My plan is to: 1) Clean up and formalize the target pre-legalization DAG combine that converts a VSELECT with a constant condition operand into a VECTOR_SHUFFLE. 2) Remove any fancy lowering from VSELECT during *legalization* relying entirely on the DAG combine to catch cases where we can match to an immediate-controlled blend instruction. One additional step that I'm not planning on but would be interested in others' opinions on: we could add an X86ISD::VSELECT or X86ISD::BLENDV which encodes a fully legalized VSELECT node. Then it would be easy to write isel patterns only in terms of this to ensure VECTOR_SHUFFLE legalization only ever forms the fully legalized construct and we can't cycle between it and VSELECT combining. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218658 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-30 02:52:28 +00:00
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Analysis
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[x86] Revert r218588, r218589, and r218600. These patches were pursuing	2014-09-30 02:52:28 +00:00
DebugInfo	Removing empty tests from failed revert	2014-09-24 21:45:26 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	[asan] don't instrument module CTORs that may be run before asan.module_ctor. This fixes asan running together -coverage	2014-09-24 22:41:55 +00:00
Integer
JitListener
Linker
LTO
MC	WinCOFFObjectWriter: optimize the string table for common suffices	2014-09-29 22:43:20 +00:00
Object
Other
TableGen	Update test case to match minor formatting change introduced in r218563.	2014-09-27 05:36:53 +00:00
tools	Update llvm-objdump’s Mach-O symbolizer code to print the name of symbol stubs.	2014-09-26 22:20:44 +00:00
Transforms	[AArch64] Improve cost model to handle sdiv by a pow-of-two.	2014-09-29 13:59:31 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg	pass environment when invoking llvm-config from lit.cfg	2014-09-24 18:37:48 +00:00
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh