Tom Stellard 4ac0136bbe Merging r200743: ...

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r200743 | michel.daenzer | 2014-02-03 23:12:38 -0800 (Mon, 03 Feb 2014) | 11 lines

R600/SI: Fix fneg for 0.0

V_ADD_F32 with source modifier does not produce -0.0 for this. Just
manipulate the sign bit directly instead.

Also add a pattern for (fneg (fabs ...)).

Fixes a bunch of bit encoding piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204643 91177308-0d34-0410-b5e6-96231b3b80d8

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AArch64

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ARM

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CPP

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Generic

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Hexagon

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Inputs

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Mips

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PowerPC

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R600

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SPARC

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SystemZ

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Thumb

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X86

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