Nadav Rotem 4b36e07487 This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139288 91177308-0d34-0410-b5e6-96231b3b80d8

2011-09-08 08:43:23 +00:00

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Alpha

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ARM

Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.

2011-09-07 02:23:42 +00:00

Blackfin

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CBackend

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CellSPU

Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.

2011-09-02 10:05:01 +00:00

CPP

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Generic

This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll

2011-09-08 08:43:23 +00:00

MBlaze

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Mips

Disable these tests harder. They're XFAIL'd, but that means they still run, and

2011-09-06 22:08:18 +00:00

MSP430

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PowerPC

Split the init.trampoline intrinsic, which currently combines GCC's

2011-09-06 13:37:06 +00:00

PTX

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SPARC

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SystemZ

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Thumb

Disable these tests harder. They're XFAIL'd, but that means they still run, and

2011-09-06 22:08:18 +00:00

Thumb2

Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical

2011-08-30 01:34:54 +00:00

X86

add a testcase for the previous patch

2011-09-08 08:31:31 +00:00

XCore

Split the init.trampoline intrinsic, which currently combines GCC's

2011-09-06 13:37:06 +00:00