Evan Cheng f26ffe987c Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51667 91177308-0d34-0410-b5e6-96231b3b80d8		2008-05-29 08:22:04 +00:00
..
CallingConvLower.cpp
DAGCombiner.cpp	Add #includes to make some dependencies explicit.	2008-05-23 20:40:06 +00:00
LegalizeDAG.cpp	If the result of a BIT_CONVERT is a v1* vector, it doesn't mean its source is a v1* vector.	2008-05-16 17:19:05 +00:00
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesExpand.cpp
LegalizeTypesFloatToInt.cpp
LegalizeTypesPromote.cpp
LegalizeTypesScalarize.cpp
LegalizeTypesSplit.cpp
Makefile
ScheduleDAG.cpp	Use a better idiom to silence compiler warnings.	2008-05-14 21:08:07 +00:00
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp	Silence the compiler warning differently. The	2008-05-16 09:19:16 +00:00
SelectionDAG.cpp	Implement vector shift up / down and insert zero with ps{rl}lq / ps{rl}ldq.	2008-05-29 08:22:04 +00:00
SelectionDAGISel.cpp	Use isSingleValueType instead of isFirstClassType to	2008-05-23 00:34:04 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.	2008-05-12 23:04:07 +00:00