mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 03:30:28 +00:00
172862a2a7
All of these "subreg32" modifier instructions are handled explicitly by the MCInst lowering phase. If they got to the asmprinter, they would explode. They should eventually be replace with correct use of subregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84526 91177308-0d34-0410-b5e6-96231b3b80d8
112 lines
3.3 KiB
C++
112 lines
3.3 KiB
C++
//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file includes code for rendering MCInst instances as AT&T-style
|
|
// assembly.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#define DEBUG_TYPE "asm-printer"
|
|
#include "X86ATTInstPrinter.h"
|
|
#include "llvm/MC/MCInst.h"
|
|
#include "llvm/MC/MCAsmInfo.h"
|
|
#include "llvm/MC/MCExpr.h"
|
|
#include "llvm/Support/ErrorHandling.h"
|
|
#include "llvm/Support/FormattedStream.h"
|
|
#include "X86GenInstrNames.inc"
|
|
using namespace llvm;
|
|
|
|
// Include the auto-generated portion of the assembly writer.
|
|
#define MachineInstr MCInst
|
|
#define NO_ASM_WRITER_BOILERPLATE
|
|
#include "X86GenAsmWriter.inc"
|
|
#undef MachineInstr
|
|
|
|
void X86ATTInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
|
|
|
|
void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
|
|
switch (MI->getOperand(Op).getImm()) {
|
|
default: llvm_unreachable("Invalid ssecc argument!");
|
|
case 0: O << "eq"; break;
|
|
case 1: O << "lt"; break;
|
|
case 2: O << "le"; break;
|
|
case 3: O << "unord"; break;
|
|
case 4: O << "neq"; break;
|
|
case 5: O << "nlt"; break;
|
|
case 6: O << "nle"; break;
|
|
case 7: O << "ord"; break;
|
|
}
|
|
}
|
|
|
|
/// print_pcrel_imm - This is used to print an immediate value that ends up
|
|
/// being encoded as a pc-relative value. These print slightly differently, for
|
|
/// example, a $ is not emitted.
|
|
void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
if (Op.isImm())
|
|
O << Op.getImm();
|
|
else {
|
|
assert(Op.isExpr() && "unknown pcrel immediate operand");
|
|
Op.getExpr()->print(O, &MAI);
|
|
}
|
|
}
|
|
|
|
void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo) {
|
|
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
if (Op.isReg()) {
|
|
O << '%' << getRegisterName(Op.getReg());
|
|
} else if (Op.isImm()) {
|
|
O << '$' << Op.getImm();
|
|
} else {
|
|
assert(Op.isExpr() && "unknown operand kind in printOperand");
|
|
O << '$';
|
|
Op.getExpr()->print(O, &MAI);
|
|
}
|
|
}
|
|
|
|
void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
|
|
const MCOperand &BaseReg = MI->getOperand(Op);
|
|
const MCOperand &IndexReg = MI->getOperand(Op+2);
|
|
const MCOperand &DispSpec = MI->getOperand(Op+3);
|
|
|
|
if (DispSpec.isImm()) {
|
|
int64_t DispVal = DispSpec.getImm();
|
|
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
|
|
O << DispVal;
|
|
} else {
|
|
assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
|
|
DispSpec.getExpr()->print(O, &MAI);
|
|
}
|
|
|
|
if (IndexReg.getReg() || BaseReg.getReg()) {
|
|
O << '(';
|
|
if (BaseReg.getReg())
|
|
printOperand(MI, Op);
|
|
|
|
if (IndexReg.getReg()) {
|
|
O << ',';
|
|
printOperand(MI, Op+2);
|
|
unsigned ScaleVal = MI->getOperand(Op+1).getImm();
|
|
if (ScaleVal != 1)
|
|
O << ',' << ScaleVal;
|
|
}
|
|
O << ')';
|
|
}
|
|
}
|
|
|
|
void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op) {
|
|
// If this has a segment register, print it.
|
|
if (MI->getOperand(Op+4).getReg()) {
|
|
printOperand(MI, Op+4);
|
|
O << ':';
|
|
}
|
|
printLeaMemReference(MI, Op);
|
|
}
|