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https://github.com/c64scene-ar/llvm-6502.git
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4b6ee7a352
Patch by Reed Kotler at Mips Technologies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140886 91177308-0d34-0410-b5e6-96231b3b80d8
118 lines
3.5 KiB
C++
118 lines
3.5 KiB
C++
#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Object/MachOFormat.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class MipsELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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MipsELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
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bool HasRelocationAddend)
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: MCELFObjectTargetWriter(is64Bit, OSType, EMachine,
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HasRelocationAddend) {}
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};
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class MipsAsmBackend : public MCAsmBackend {
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public:
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MipsAsmBackend(const Target &T)
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: MCAsmBackend() {}
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unsigned getNumFixupKinds() const {
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return 1; //tbd
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}
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/// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
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/// data fragment, at the offset specified by the fixup and following the
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/// fixup kind as appropriate.
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void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const {
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}
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/// @name Target Relaxation Interfaces
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/// @{
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/// MayNeedRelaxation - Check whether the given instruction may need
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/// relaxation.
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///
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/// \param Inst - The instruction to test.
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bool MayNeedRelaxation(const MCInst &Inst) const {
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return false;
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}
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/// RelaxInstruction - Relax the instruction in the given fragment to the next
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/// wider instruction.
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///
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/// \param Inst - The instruction to relax, which may be the same as the
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/// output.
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/// \parm Res [output] - On return, the relaxed instruction.
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void RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
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}
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/// @}
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/// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given
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/// output. If the target cannot generate such a sequence, it should return an
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/// error.
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///
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/// \return - True on success.
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bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
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return false;
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}
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};
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class MipsEB_AsmBackend : public MipsAsmBackend {
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public:
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Triple::OSType OSType;
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MipsEB_AsmBackend(const Target &T, Triple::OSType _OSType)
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: MipsAsmBackend(T), OSType(_OSType) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createELFObjectWriter(createELFObjectTargetWriter(),
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OS, /*IsLittleEndian*/ false);
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}
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MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
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return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false);
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}
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};
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class MipsEL_AsmBackend : public MipsAsmBackend {
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public:
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Triple::OSType OSType;
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MipsEL_AsmBackend(const Target &T, Triple::OSType _OSType)
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: MipsAsmBackend(T), OSType(_OSType) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createELFObjectWriter(createELFObjectTargetWriter(),
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OS, /*IsLittleEndian*/ true);
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}
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MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
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return new MipsELFObjectWriter(false, OSType, ELF::EM_MIPS, false);
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}
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};
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}
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MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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// just return little endian for now
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//
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return new MipsEL_AsmBackend(T, Triple(TT).getOS());
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}
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