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Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215558 91177308-0d34-0410-b5e6-96231b3b80d8
186 lines
6.5 KiB
C++
186 lines
6.5 KiB
C++
//===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAGSDNodes class, which implements
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// scheduling for an SDNode-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
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#define LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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namespace llvm {
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/// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
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///
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/// Edges between SUnits are initially based on edges in the SelectionDAG,
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/// and additional edges can be added by the schedulers as heuristics.
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/// SDNodes such as Constants, Registers, and a few others that are not
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/// interesting to schedulers are not allocated SUnits.
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///
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/// SDNodes with MVT::Glue operands are grouped along with the flagged
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/// nodes into a single SUnit so that they are scheduled together.
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///
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/// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
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/// edges. Physical register dependence information is not carried in
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/// the DAG and must be handled explicitly by schedulers.
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///
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class ScheduleDAGSDNodes : public ScheduleDAG {
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public:
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MachineBasicBlock *BB;
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SelectionDAG *DAG; // DAG of the current basic block
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const InstrItineraryData *InstrItins;
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/// The schedule. Null SUnit*'s represent noop instructions.
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std::vector<SUnit*> Sequence;
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explicit ScheduleDAGSDNodes(MachineFunction &mf);
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virtual ~ScheduleDAGSDNodes() {}
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/// Run - perform scheduling.
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///
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void Run(SelectionDAG *dag, MachineBasicBlock *bb);
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/// isPassiveNode - Return true if the node is a non-scheduled leaf.
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///
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static bool isPassiveNode(SDNode *Node) {
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if (isa<ConstantSDNode>(Node)) return true;
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if (isa<ConstantFPSDNode>(Node)) return true;
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if (isa<RegisterSDNode>(Node)) return true;
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if (isa<RegisterMaskSDNode>(Node)) return true;
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if (isa<GlobalAddressSDNode>(Node)) return true;
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if (isa<BasicBlockSDNode>(Node)) return true;
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if (isa<FrameIndexSDNode>(Node)) return true;
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if (isa<ConstantPoolSDNode>(Node)) return true;
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if (isa<TargetIndexSDNode>(Node)) return true;
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if (isa<JumpTableSDNode>(Node)) return true;
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if (isa<ExternalSymbolSDNode>(Node)) return true;
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if (isa<BlockAddressSDNode>(Node)) return true;
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if (Node->getOpcode() == ISD::EntryToken ||
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isa<MDNodeSDNode>(Node)) return true;
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return false;
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}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *newSUnit(SDNode *N);
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/// Clone - Creates a clone of the specified SUnit. It does not copy the
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/// predecessors / successors info nor the temporary scheduling states.
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///
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SUnit *Clone(SUnit *N);
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/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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/// are input. This SUnit graph is similar to the SelectionDAG, but
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/// excludes nodes that aren't interesting to scheduling, and represents
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/// flagged together nodes with a single SUnit.
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void BuildSchedGraph(AliasAnalysis *AA);
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/// InitVRegCycleFlag - Set isVRegCycle if this node's single use is
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/// CopyToReg and its only active data operands are CopyFromReg within a
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/// single block loop.
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///
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void InitVRegCycleFlag(SUnit *SU);
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/// InitNumRegDefsLeft - Determine the # of regs defined by this node.
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///
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void InitNumRegDefsLeft(SUnit *SU);
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/// computeLatency - Compute node latency.
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///
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virtual void computeLatency(SUnit *SU);
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virtual void computeOperandLatency(SDNode *Def, SDNode *Use,
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unsigned OpIdx, SDep& dep) const;
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/// Schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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virtual void Schedule() = 0;
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/// VerifyScheduledSequence - Verify that all SUnits are scheduled and
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/// consistent with the Sequence of scheduled instructions.
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void VerifyScheduledSequence(bool isBottomUp);
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/// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
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/// according to the order specified in Sequence.
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///
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virtual MachineBasicBlock*
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EmitSchedule(MachineBasicBlock::iterator &InsertPos);
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void dumpNode(const SUnit *SU) const override;
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void dumpSchedule() const;
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std::string getGraphNodeLabel(const SUnit *SU) const override;
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std::string getDAGName() const override;
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virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
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/// RegDefIter - In place iteration over the values defined by an
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/// SUnit. This does not need copies of the iterator or any other STLisms.
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/// The iterator creates itself, rather than being provided by the SchedDAG.
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class RegDefIter {
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const ScheduleDAGSDNodes *SchedDAG;
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const SDNode *Node;
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unsigned DefIdx;
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unsigned NodeNumDefs;
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MVT ValueType;
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public:
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RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
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bool IsValid() const { return Node != nullptr; }
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MVT GetValue() const {
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assert(IsValid() && "bad iterator");
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return ValueType;
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}
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const SDNode *GetNode() const {
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return Node;
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}
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unsigned GetIdx() const {
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return DefIdx-1;
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}
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void Advance();
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private:
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void InitNodeNumDefs();
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};
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protected:
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/// ForceUnitLatencies - Return true if all scheduling edges should be given
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/// a latency value of one. The default is to return false; schedulers may
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/// override this as needed.
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virtual bool forceUnitLatencies() const { return false; }
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private:
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/// ClusterNeighboringLoads - Cluster loads from "near" addresses into
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/// combined SUnits.
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void ClusterNeighboringLoads(SDNode *Node);
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/// ClusterNodes - Cluster certain nodes which should be scheduled together.
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///
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void ClusterNodes();
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/// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
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void BuildSchedUnits();
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void AddSchedEdges();
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void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
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MachineBasicBlock::iterator InsertPos);
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};
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}
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#endif
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