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4cef3fb022
The existing code in PPCTargetLowering::LowerMUL() for multiplying two v16i8 values assumes that vector elements are numbered in big-endian order. For little-endian targets, the vector element numbering is reversed, but the vmuleub, vmuloub, and vperm instructions still assume big-endian numbering. To account for this, we must adjust the permute control vector and reverse the order of the input registers on the vperm instruction. The existing test/CodeGen/PowerPC/vec_mul.ll is updated to be executed on powerpc64 and powerpc64le targets as well as the original powerpc (32-bit) target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210474 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.2 KiB
LLVM
64 lines
2.2 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s -check-prefix=CHECK-LE
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define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
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%tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1]
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%tmp2 = load <4 x i32>* %Y ; <<4 x i32>> [#uses=1]
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%tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp3
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}
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; CHECK-LABEL: test_v4i32:
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; CHECK: vmsumuhm
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; CHECK-NOT: mullw
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; CHECK-LE-LABEL: test_v4i32:
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; CHECK-LE: vmsumuhm
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; CHECK-LE-NOT: mullw
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define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
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%tmp = load <8 x i16>* %X ; <<8 x i16>> [#uses=1]
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%tmp2 = load <8 x i16>* %Y ; <<8 x i16>> [#uses=1]
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%tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp3
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}
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; CHECK-LABEL: test_v8i16:
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; CHECK: vmladduhm
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; CHECK-NOT: mullw
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; CHECK-LE-LABEL: test_v8i16:
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; CHECK-LE: vmladduhm
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; CHECK-LE-NOT: mullw
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define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
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%tmp = load <16 x i8>* %X ; <<16 x i8>> [#uses=1]
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%tmp2 = load <16 x i8>* %Y ; <<16 x i8>> [#uses=1]
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%tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp3
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}
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; CHECK-LABEL: test_v16i8:
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; CHECK: vmuloub
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; CHECK: vmuleub
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; CHECK-NOT: mullw
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; CHECK-LE-LABEL: test_v16i8:
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; CHECK-LE: vmuloub [[REG1:[0-9]+]]
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; CHECK-LE: vmuleub [[REG2:[0-9]+]]
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; CHECK-LE: vperm {{[0-9]+}}, [[REG2]], [[REG1]]
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; CHECK-LE-NOT: mullw
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define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
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%tmp = load <4 x float>* %X
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%tmp2 = load <4 x float>* %Y
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%tmp3 = fmul <4 x float> %tmp, %tmp2
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ret <4 x float> %tmp3
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}
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; Check the creation of a negative zero float vector by creating a vector of
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; all bits set and shifting it 31 bits to left, resulting a an vector of
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; 4 x 0x80000000 (-0.0 as float).
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; CHECK-LABEL: test_float:
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; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
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; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
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; CHECK: vmaddfp
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; CHECK-LE-LABEL: test_float:
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; CHECK-LE: vspltisw [[ZNEG:[0-9]+]], -1
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; CHECK-LE: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
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; CHECK-LE: vmaddfp
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