mirror of
https://github.com/c64scene-ar/llvm-6502.git
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fabdd6632a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200962 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
6.3 KiB
C++
140 lines
6.3 KiB
C++
//===-- SparcELFObjectWriter.cpp - Sparc ELF Writer -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SparcFixupKinds.h"
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#include "MCTargetDesc/SparcMCExpr.h"
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#include "MCTargetDesc/SparcMCTargetDesc.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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namespace {
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class SparcELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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SparcELFObjectWriter(bool Is64Bit, uint8_t OSABI)
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: MCELFObjectTargetWriter(Is64Bit, OSABI,
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Is64Bit ? ELF::EM_SPARCV9 : ELF::EM_SPARC,
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/*HasRelocationAddend*/ true) {}
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virtual ~SparcELFObjectWriter() {}
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protected:
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virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
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bool IsPCRel, bool IsRelocWithSymbol,
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int64_t Addend) const;
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virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
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const MCValue &Target,
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const MCFragment &F,
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const MCFixup &Fixup,
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bool IsPCRel) const;
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};
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}
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unsigned SparcELFObjectWriter::GetRelocType(const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel,
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bool IsRelocWithSymbol,
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int64_t Addend) const {
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if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Fixup.getValue())) {
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if (SExpr->getKind() == SparcMCExpr::VK_Sparc_R_DISP32)
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return ELF::R_SPARC_DISP32;
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}
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if (IsPCRel) {
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switch((unsigned)Fixup.getKind()) {
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default:
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llvm_unreachable("Unimplemented fixup -> relocation");
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case FK_Data_1: return ELF::R_SPARC_DISP8;
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case FK_Data_2: return ELF::R_SPARC_DISP16;
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case FK_Data_4: return ELF::R_SPARC_DISP32;
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case FK_Data_8: return ELF::R_SPARC_DISP64;
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case Sparc::fixup_sparc_call30: return ELF::R_SPARC_WDISP30;
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case Sparc::fixup_sparc_br22: return ELF::R_SPARC_WDISP22;
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case Sparc::fixup_sparc_br19: return ELF::R_SPARC_WDISP19;
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case Sparc::fixup_sparc_pc22: return ELF::R_SPARC_PC22;
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case Sparc::fixup_sparc_pc10: return ELF::R_SPARC_PC10;
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case Sparc::fixup_sparc_wplt30: return ELF::R_SPARC_WPLT30;
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}
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}
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switch((unsigned)Fixup.getKind()) {
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default:
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llvm_unreachable("Unimplemented fixup -> relocation");
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case FK_Data_1: return ELF::R_SPARC_8;
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case FK_Data_2: return ((Fixup.getOffset() % 2)
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? ELF::R_SPARC_UA16
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: ELF::R_SPARC_16);
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case FK_Data_4: return ((Fixup.getOffset() % 4)
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? ELF::R_SPARC_UA32
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: ELF::R_SPARC_32);
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case FK_Data_8: return ((Fixup.getOffset() % 8)
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? ELF::R_SPARC_UA64
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: ELF::R_SPARC_64);
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case Sparc::fixup_sparc_hi22: return ELF::R_SPARC_HI22;
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case Sparc::fixup_sparc_lo10: return ELF::R_SPARC_LO10;
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case Sparc::fixup_sparc_h44: return ELF::R_SPARC_H44;
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case Sparc::fixup_sparc_m44: return ELF::R_SPARC_M44;
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case Sparc::fixup_sparc_l44: return ELF::R_SPARC_L44;
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case Sparc::fixup_sparc_hh: return ELF::R_SPARC_HH22;
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case Sparc::fixup_sparc_hm: return ELF::R_SPARC_HM10;
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case Sparc::fixup_sparc_got22: return ELF::R_SPARC_GOT22;
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case Sparc::fixup_sparc_got10: return ELF::R_SPARC_GOT10;
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case Sparc::fixup_sparc_tls_gd_hi22: return ELF::R_SPARC_TLS_GD_HI22;
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case Sparc::fixup_sparc_tls_gd_lo10: return ELF::R_SPARC_TLS_GD_LO10;
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case Sparc::fixup_sparc_tls_gd_add: return ELF::R_SPARC_TLS_GD_ADD;
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case Sparc::fixup_sparc_tls_gd_call: return ELF::R_SPARC_TLS_GD_CALL;
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case Sparc::fixup_sparc_tls_ldm_hi22: return ELF::R_SPARC_TLS_LDM_HI22;
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case Sparc::fixup_sparc_tls_ldm_lo10: return ELF::R_SPARC_TLS_LDM_LO10;
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case Sparc::fixup_sparc_tls_ldm_add: return ELF::R_SPARC_TLS_LDM_ADD;
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case Sparc::fixup_sparc_tls_ldm_call: return ELF::R_SPARC_TLS_LDM_CALL;
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case Sparc::fixup_sparc_tls_ldo_hix22: return ELF::R_SPARC_TLS_LDO_HIX22;
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case Sparc::fixup_sparc_tls_ldo_lox10: return ELF::R_SPARC_TLS_LDO_LOX10;
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case Sparc::fixup_sparc_tls_ldo_add: return ELF::R_SPARC_TLS_LDO_ADD;
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case Sparc::fixup_sparc_tls_ie_hi22: return ELF::R_SPARC_TLS_IE_HI22;
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case Sparc::fixup_sparc_tls_ie_lo10: return ELF::R_SPARC_TLS_IE_LO10;
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case Sparc::fixup_sparc_tls_ie_ld: return ELF::R_SPARC_TLS_IE_LD;
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case Sparc::fixup_sparc_tls_ie_ldx: return ELF::R_SPARC_TLS_IE_LDX;
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case Sparc::fixup_sparc_tls_ie_add: return ELF::R_SPARC_TLS_IE_ADD;
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case Sparc::fixup_sparc_tls_le_hix22: return ELF::R_SPARC_TLS_LE_HIX22;
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case Sparc::fixup_sparc_tls_le_lox10: return ELF::R_SPARC_TLS_LE_LOX10;
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}
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return ELF::R_SPARC_NONE;
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}
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const MCSymbol *SparcELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm,
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const MCValue &Target,
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const MCFragment &F,
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const MCFixup &Fixup,
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bool IsPCRel) const {
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if (!Target.getSymA())
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return NULL;
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switch((unsigned)Fixup.getKind()) {
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default: break;
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case Sparc::fixup_sparc_got22:
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case Sparc::fixup_sparc_got10:
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return &Target.getSymA()->getSymbol().AliasedSymbol();
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}
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return NULL;
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}
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MCObjectWriter *llvm::createSparcELFObjectWriter(raw_ostream &OS,
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bool Is64Bit,
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uint8_t OSABI) {
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MCELFObjectTargetWriter *MOTW = new SparcELFObjectWriter(Is64Bit, OSABI);
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return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false);
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}
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