llvm-6502/lib
Evan Cheng 3c82cab9aa GetRegForReload() now keeps track which registers have been considered and rejected during its quest to find a suitable reload register. This avoids an infinite loop in case like this:
t1 := op t2, t3
  t2 <- assigned r0 for use by the reload but ended up reuse r1
  t3 <- assigned r1 for use by the reload but ended up reuse r0
  t1 <- desires r1
        sees r1 is taken by t2, tries t2's reload register r0
        sees r0 is taken by t3, tries t3's reload register r1
        sees r1 is taken by t2, tries t2's reload register r0 ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33382 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19 22:40:14 +00:00
..
Analysis For PR1043: 2007-01-19 21:13:56 +00:00
Archive For PR1050: 2006-12-15 19:44:51 +00:00
AsmParser Regenerate. 2007-01-17 02:48:45 +00:00
Bytecode Back out last changes for dataLayout. Much more work is needed. 2007-01-19 00:07:16 +00:00
CodeGen GetRegForReload() now keeps track which registers have been considered and rejected during its quest to find a suitable reload register. This avoids an infinite loop in case like this: 2007-01-19 22:40:14 +00:00
Debugger
ExecutionEngine For PR1043: 2007-01-19 21:13:56 +00:00
Linker For PR1064: 2007-01-12 07:05:14 +00:00
Support For PR1043: 2007-01-19 21:13:56 +00:00
System Unbreak Darwin. 2007-01-19 22:04:24 +00:00
Target For PR1043: 2007-01-19 21:13:56 +00:00
Transforms For this transform: store V, (cast P) -> store (cast V), P 2007-01-19 21:20:31 +00:00
VMCore Remove dead methods in the ValTypes. 2007-01-19 21:25:12 +00:00
Makefile