mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
a70f28ce7d
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
1.5 KiB
LLVM
67 lines
1.5 KiB
LLVM
; Ensure that floating point operations are lowered to function calls when the
|
|
; FPU is not available in the hardware and that function calls are not used
|
|
; when the FPU is available in the hardware.
|
|
;
|
|
; RUN: llc < %s -march=mblaze | FileCheck -check-prefix=FUN %s
|
|
; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
|
|
|
|
define float @test_add(float %a, float %b) {
|
|
; FUN: test_add:
|
|
; FPU: test_add:
|
|
|
|
%tmp.1 = fadd float %a, %b
|
|
; FUN-NOT: fadd
|
|
; FUN: brlid
|
|
; FPU-NOT: brlid
|
|
; FPU: fadd
|
|
|
|
ret float %tmp.1
|
|
; FUN: rtsd
|
|
; FPU: rtsd
|
|
}
|
|
|
|
define float @test_sub(float %a, float %b) {
|
|
; FUN: test_sub:
|
|
; FPU: test_sub:
|
|
|
|
%tmp.1 = fsub float %a, %b
|
|
; FUN-NOT: frsub
|
|
; FUN: brlid
|
|
; FPU-NOT: brlid
|
|
; FPU: frsub
|
|
|
|
ret float %tmp.1
|
|
; FUN: rtsd
|
|
; FPU: rtsd
|
|
}
|
|
|
|
define float @test_mul(float %a, float %b) {
|
|
; FUN: test_mul:
|
|
; FPU: test_mul:
|
|
|
|
%tmp.1 = fmul float %a, %b
|
|
; FUN-NOT: fmul
|
|
; FUN: brlid
|
|
; FPU-NOT: brlid
|
|
; FPU: fmul
|
|
|
|
ret float %tmp.1
|
|
; FUN: rtsd
|
|
; FPU: rtsd
|
|
}
|
|
|
|
define float @test_div(float %a, float %b) {
|
|
; FUN: test_div:
|
|
; FPU: test_div:
|
|
|
|
%tmp.1 = fdiv float %a, %b
|
|
; FUN-NOT: fdiv
|
|
; FUN: brlid
|
|
; FPU-NOT: brlid
|
|
; FPU: fdiv
|
|
|
|
ret float %tmp.1
|
|
; FUN: rtsd
|
|
; FPU: rtsd
|
|
}
|