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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118397 91177308-0d34-0410-b5e6-96231b3b80d8
208 lines
6.9 KiB
C++
208 lines
6.9 KiB
C++
//===-- PTXISelLowering.cpp - PTX DAG Lowering Implementation -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PTXTargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXISelLowering.h"
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#include "PTXMachineFunctionInfo.h"
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#include "PTXRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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using namespace llvm;
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PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
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: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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// Set up the register classes.
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addRegisterClass(MVT::i1, PTX::PredsRegisterClass);
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addRegisterClass(MVT::i32, PTX::RRegs32RegisterClass);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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}
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const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: llvm_unreachable("Unknown opcode");
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case PTXISD::EXIT: return "PTXISD::EXIT";
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case PTXISD::RET: return "PTXISD::RET";
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}
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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struct argmap_entry {
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MVT::SimpleValueType VT;
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TargetRegisterClass *RC;
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TargetRegisterClass::iterator loc;
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argmap_entry(MVT::SimpleValueType _VT, TargetRegisterClass *_RC)
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: VT(_VT), RC(_RC), loc(_RC->begin()) {}
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void reset() { loc = RC->begin(); }
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bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
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} argmap[] = {
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argmap_entry(MVT::i1, PTX::PredsRegisterClass),
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argmap_entry(MVT::i32, PTX::RRegs32RegisterClass)
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};
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} // end anonymous namespace
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static SDValue lower_kernel_argument(int i,
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SDValue Chain,
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DebugLoc dl,
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MVT::SimpleValueType VT,
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argmap_entry *entry,
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SelectionDAG &DAG,
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unsigned *argreg) {
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// TODO
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llvm_unreachable("Not implemented yet");
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}
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static SDValue lower_device_argument(int i,
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SDValue Chain,
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DebugLoc dl,
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MVT::SimpleValueType VT,
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argmap_entry *entry,
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SelectionDAG &DAG,
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unsigned *argreg) {
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MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
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unsigned preg = *++(entry->loc); // allocate start from register 1
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unsigned vreg = RegInfo.createVirtualRegister(entry->RC);
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RegInfo.addLiveIn(preg, vreg);
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*argreg = preg;
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return DAG.getCopyFromReg(Chain, dl, vreg, VT);
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}
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typedef SDValue (*lower_argument_func)(int i,
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SDValue Chain,
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DebugLoc dl,
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MVT::SimpleValueType VT,
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argmap_entry *entry,
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SelectionDAG &DAG,
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unsigned *argreg);
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SDValue PTXTargetLowering::
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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if (isVarArg) llvm_unreachable("PTX does not support varargs");
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MachineFunction &MF = DAG.getMachineFunction();
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PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
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lower_argument_func lower_argument;
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention");
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break;
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case CallingConv::PTX_Kernel:
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MFI->setKernel();
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lower_argument = lower_kernel_argument;
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break;
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case CallingConv::PTX_Device:
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MFI->setKernel(false);
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lower_argument = lower_device_argument;
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break;
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}
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// Reset argmap before allocation
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for (struct argmap_entry *i = argmap, *e = argmap + array_lengthof(argmap);
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i != e; ++ i)
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i->reset();
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for (int i = 0, e = Ins.size(); i != e; ++ i) {
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MVT::SimpleValueType VT = Ins[i].VT.SimpleTy;
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struct argmap_entry *entry = std::find(argmap,
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argmap + array_lengthof(argmap), VT);
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if (entry == argmap + array_lengthof(argmap))
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llvm_unreachable("Type of argument is not supported");
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unsigned reg;
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SDValue arg = lower_argument(i, Chain, dl, VT, entry, DAG, ®);
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InVals.push_back(arg);
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if (!MFI->isDoneAddArg())
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MFI->addArgReg(reg);
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}
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// Make sure we don't add argument registers twice
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if (!MFI->isDoneAddArg())
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MFI->doneAddArg();
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return Chain;
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}
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SDValue PTXTargetLowering::
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl,
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SelectionDAG &DAG) const {
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if (isVarArg) llvm_unreachable("PTX does not support varargs");
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention.");
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case CallingConv::PTX_Kernel:
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assert(Outs.size() == 0 && "Kernel must return void.");
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return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
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case CallingConv::PTX_Device:
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assert(Outs.size() <= 1 && "Can at most return one value.");
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break;
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}
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// PTX_Device
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// return void
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if (Outs.size() == 0)
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return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
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assert(Outs[0].VT == MVT::i32 && "Can return only basic types");
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SDValue Flag;
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unsigned reg = PTX::R0;
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MachineFunction &MF = DAG.getMachineFunction();
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PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
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MFI->setRetReg(reg);
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function
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if (DAG.getMachineFunction().getRegInfo().liveout_empty())
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DAG.getMachineFunction().getRegInfo().addLiveOut(reg);
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// Copy the result values into the output registers
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Chain = DAG.getCopyToReg(Chain, dl, reg, OutVals[0], Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad
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Flag = Chain.getValue(1);
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return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);
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}
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