llvm-6502/test/CodeGen/XCore/addsub64.ll
Stephen Lin 8b2b8a1835 Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.
This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 06:24:09 +00:00

60 lines
1.2 KiB
LLVM

; RUN: llc < %s -march=xcore | FileCheck %s
define i64 @add64(i64 %a, i64 %b) {
%result = add i64 %a, %b
ret i64 %result
}
; CHECK: add64
; CHECK: ldc r11, 0
; CHECK-NEXT: ladd r2, r0, r0, r2, r11
; CHECK-NEXT: ladd r2, r1, r1, r3, r2
; CHECK-NEXT: retsp 0
define i64 @sub64(i64 %a, i64 %b) {
%result = sub i64 %a, %b
ret i64 %result
}
; CHECK: sub64
; CHECK: ldc r11, 0
; CHECK-NEXT: lsub r2, r0, r0, r2, r11
; CHECK-NEXT: lsub r2, r1, r1, r3, r2
; CHECK-NEXT: retsp 0
define i64 @maccu(i64 %a, i32 %b, i32 %c) {
entry:
%0 = zext i32 %b to i64
%1 = zext i32 %c to i64
%2 = mul i64 %1, %0
%3 = add i64 %2, %a
ret i64 %3
}
; CHECK-LABEL: maccu:
; CHECK: maccu r1, r0, r3, r2
; CHECK-NEXT: retsp 0
define i64 @maccs(i64 %a, i32 %b, i32 %c) {
entry:
%0 = sext i32 %b to i64
%1 = sext i32 %c to i64
%2 = mul i64 %1, %0
%3 = add i64 %2, %a
ret i64 %3
}
; CHECK-LABEL: maccs:
; CHECK: maccs r1, r0, r3, r2
; CHECK-NEXT: retsp 0
define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) {
entry:
%0 = zext i32 %a to i64
%1 = zext i32 %b to i64
%2 = zext i32 %c to i64
%3 = zext i32 %d to i64
%4 = mul i64 %1, %0
%5 = add i64 %4, %2
%6 = add i64 %5, %3
ret i64 %6
}
; CHECK-LABEL: lmul:
; CHECK: lmul r1, r0, r1, r0, r2, r3
; CHECK-NEXT: retsp 0