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Update all callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228930 91177308-0d34-0410-b5e6-96231b3b80d8
1749 lines
62 KiB
C++
1749 lines
62 KiB
C++
//===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the Hexagon target.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "hexagon-isel"
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static
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cl::opt<unsigned>
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MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
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cl::Hidden, cl::init(2),
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cl::desc("Maximum number of uses of a global address such that we still us a"
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"constant extended instruction"));
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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namespace llvm {
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void initializeHexagonDAGToDAGISelPass(PassRegistry&);
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}
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//===--------------------------------------------------------------------===//
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/// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class HexagonDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const HexagonSubtarget *Subtarget;
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// Keep a reference to HexagonTargetMachine.
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const HexagonTargetMachine& TM;
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DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
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public:
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explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(targetmachine, OptLevel), TM(targetmachine) {
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initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
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}
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bool hasNumUsesBelowThresGA(SDNode *N) const;
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SDNode *Select(SDNode *N) override;
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// Complex Pattern Selectors.
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inline bool foldGlobalAddress(SDValue &N, SDValue &R);
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inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
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bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
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bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
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bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
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bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
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bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
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bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
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bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRriU6_0(SDValue& N, SDValue &R1, SDValue &R2);
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bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
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bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
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// Complex Pattern Selectors.
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inline bool SelectAddrGA(SDValue &N, SDValue &R);
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inline bool SelectAddrGP(SDValue &N, SDValue &R);
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bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
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bool SelectAddrFI(SDValue &N, SDValue &R);
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const char *getPassName() const override {
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return "Hexagon DAG->DAG Pattern Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<HexagonSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps) override;
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bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
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SDNode *SelectLoad(SDNode *N);
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SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
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SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
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SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
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SDLoc dl);
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SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
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SDLoc dl);
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SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
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SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
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SDNode *SelectStore(SDNode *N);
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SDNode *SelectSHL(SDNode *N);
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SDNode *SelectSelect(SDNode *N);
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SDNode *SelectTruncate(SDNode *N);
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SDNode *SelectMul(SDNode *N);
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SDNode *SelectZeroExtend(SDNode *N);
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SDNode *SelectIntrinsicWOChain(SDNode *N);
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SDNode *SelectIntrinsicWChain(SDNode *N);
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SDNode *SelectConstant(SDNode *N);
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SDNode *SelectConstantFP(SDNode *N);
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SDNode *SelectAdd(SDNode *N);
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bool isConstExtProfitable(SDNode *N) const;
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// XformMskToBitPosU5Imm - Returns the bit position which
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// the single bit 32 bit mask represents.
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// Used in Clr and Set bit immediate memops.
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SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
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int32_t bitPos;
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bitPos = Log2_32(Imm);
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assert(bitPos >= 0 && bitPos < 32 &&
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"Constant out of range for 32 BitPos Memops");
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return CurDAG->getTargetConstant(bitPos, MVT::i32);
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}
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// XformMskToBitPosU4Imm - Returns the bit position which the single bit 16 bit
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// mask represents. Used in Clr and Set bit immediate memops.
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SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
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return XformMskToBitPosU5Imm(Imm);
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}
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// XformMskToBitPosU3Imm - Returns the bit position which the single bit 8 bit
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// mask represents. Used in Clr and Set bit immediate memops.
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SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
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return XformMskToBitPosU5Imm(Imm);
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}
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// Return true if there is exactly one bit set in V, i.e., if V is one of the
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// following integers: 2^0, 2^1, ..., 2^31.
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bool ImmIsSingleBit(uint32_t v) const {
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return isPowerOf2_32(v);
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}
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// XformM5ToU5Imm - Return a target constant with the specified value, of type
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// i32 where the negative literal is transformed into a positive literal for
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// use in -= memops.
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inline SDValue XformM5ToU5Imm(signed Imm) {
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assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
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return CurDAG->getTargetConstant( - Imm, MVT::i32);
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}
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// XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
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// [1..128], used in cmpb.gtu instructions.
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inline SDValue XformU7ToU7M1Imm(signed Imm) {
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assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
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return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
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}
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// XformS8ToS8M1Imm - Return a target constant decremented by 1.
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inline SDValue XformSToSM1Imm(signed Imm) {
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return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
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}
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// XformU8ToU8M1Imm - Return a target constant decremented by 1.
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inline SDValue XformUToUM1Imm(unsigned Imm) {
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assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
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return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
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}
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// XformSToSM2Imm - Return a target constant decremented by 2.
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inline SDValue XformSToSM2Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
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}
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// XformSToSM3Imm - Return a target constant decremented by 3.
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inline SDValue XformSToSM3Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
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}
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// Include the pieces autogenerated from the target description.
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#include "HexagonGenDAGISel.inc"
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private:
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bool isValueExtension(SDValue const &Val, unsigned FromBits, SDValue &Src);
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};
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} // end anonymous namespace
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/// createHexagonISelDag - This pass converts a legalized DAG into a
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/// Hexagon-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new HexagonDAGToDAGISel(TM, OptLevel);
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}
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static void initializePassOnce(PassRegistry &Registry) {
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const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
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PassInfo *PI = new PassInfo(Name, "hexagon-isel",
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&SelectionDAGISel::ID, nullptr, false, false);
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Registry.registerPass(*PI, true);
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}
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void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
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CALL_ONCE_INITIALIZATION(initializePassOnce)
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}
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static bool IsS11_0_Offset(SDNode * S) {
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ConstantSDNode *N = cast<ConstantSDNode>(S);
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// immS16 predicate - True if the immediate fits in a 16-bit sign extended
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// field.
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<11>(v);
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}
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static bool IsS11_1_Offset(SDNode * S) {
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ConstantSDNode *N = cast<ConstantSDNode>(S);
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// immS16 predicate - True if the immediate fits in a 16-bit sign extended
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// field.
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<11,1>(v);
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}
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static bool IsS11_2_Offset(SDNode * S) {
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ConstantSDNode *N = cast<ConstantSDNode>(S);
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// immS16 predicate - True if the immediate fits in a 16-bit sign extended
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// field.
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<11,2>(v);
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}
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static bool IsS11_3_Offset(SDNode * S) {
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ConstantSDNode *N = cast<ConstantSDNode>(S);
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// immS16 predicate - True if the immediate fits in a 16-bit sign extended
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// field.
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedInt<11,3>(v);
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}
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static bool IsU6_0_Offset(SDNode * S) {
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ConstantSDNode *N = cast<ConstantSDNode>(S);
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// u6 predicate - True if the immediate fits in a 6-bit unsigned extended
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// field.
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<6>(v);
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}
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static bool IsU6_1_Offset(SDNode * S) {
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ConstantSDNode *N = cast<ConstantSDNode>(S);
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// u6 predicate - True if the immediate fits in a 6-bit unsigned extended
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// field.
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<6,1>(v);
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}
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static bool IsU6_2_Offset(SDNode * S) {
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ConstantSDNode *N = cast<ConstantSDNode>(S);
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// u6 predicate - True if the immediate fits in a 6-bit unsigned extended
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// field.
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int64_t v = (int64_t)N->getSExtValue();
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return isShiftedUInt<6,2>(v);
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}
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// Intrinsics that return a a predicate.
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static unsigned doesIntrinsicReturnPredicate(unsigned ID)
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{
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switch (ID) {
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default:
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return 0;
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case Intrinsic::hexagon_C2_cmpeq:
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case Intrinsic::hexagon_C2_cmpgt:
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case Intrinsic::hexagon_C2_cmpgtu:
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case Intrinsic::hexagon_C2_cmpgtup:
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case Intrinsic::hexagon_C2_cmpgtp:
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case Intrinsic::hexagon_C2_cmpeqp:
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case Intrinsic::hexagon_C2_bitsset:
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case Intrinsic::hexagon_C2_bitsclr:
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case Intrinsic::hexagon_C2_cmpeqi:
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case Intrinsic::hexagon_C2_cmpgti:
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case Intrinsic::hexagon_C2_cmpgtui:
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case Intrinsic::hexagon_C2_cmpgei:
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case Intrinsic::hexagon_C2_cmpgeui:
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case Intrinsic::hexagon_C2_cmplt:
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case Intrinsic::hexagon_C2_cmpltu:
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case Intrinsic::hexagon_C2_bitsclri:
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case Intrinsic::hexagon_C2_and:
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case Intrinsic::hexagon_C2_or:
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case Intrinsic::hexagon_C2_xor:
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case Intrinsic::hexagon_C2_andn:
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case Intrinsic::hexagon_C2_not:
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case Intrinsic::hexagon_C2_orn:
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case Intrinsic::hexagon_C2_pxfer_map:
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case Intrinsic::hexagon_C2_any8:
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case Intrinsic::hexagon_C2_all8:
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case Intrinsic::hexagon_A2_vcmpbeq:
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case Intrinsic::hexagon_A2_vcmpbgtu:
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case Intrinsic::hexagon_A2_vcmpheq:
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case Intrinsic::hexagon_A2_vcmphgt:
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case Intrinsic::hexagon_A2_vcmphgtu:
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case Intrinsic::hexagon_A2_vcmpweq:
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case Intrinsic::hexagon_A2_vcmpwgt:
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case Intrinsic::hexagon_A2_vcmpwgtu:
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case Intrinsic::hexagon_C2_tfrrp:
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case Intrinsic::hexagon_S2_tstbit_i:
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case Intrinsic::hexagon_S2_tstbit_r:
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return 1;
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}
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}
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static bool OffsetFitsS11(EVT MemType, int64_t Offset) {
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if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
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return true;
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}
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if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
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return true;
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}
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if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
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return true;
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}
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if (MemType == MVT::i8 && isInt<11>(Offset)) {
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return true;
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}
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return false;
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}
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//
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// Try to lower loads of GlobalAdresses into base+offset loads. Custom
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// lowering for GlobalAddress nodes has already turned it into a
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// CONST32.
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//
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SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
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SDValue Chain = LD->getChain();
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SDNode* Const32 = LD->getBasePtr().getNode();
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unsigned Opcode = 0;
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if (Const32->getOpcode() == HexagonISD::CONST32 &&
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ISD::isNormalLoad(LD)) {
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SDValue Base = Const32->getOperand(0);
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EVT LoadedVT = LD->getMemoryVT();
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int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
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if (Offset != 0 && OffsetFitsS11(LoadedVT, Offset)) {
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MVT PointerTy = getTargetLowering()->getPointerTy();
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const GlobalValue* GV =
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cast<GlobalAddressSDNode>(Base)->getGlobal();
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SDValue TargAddr =
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CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
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SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
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dl, PointerTy,
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TargAddr);
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// Figure out base + offset opcode
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if (LoadedVT == MVT::i64) Opcode = Hexagon::L2_loadrd_io;
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else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io;
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else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;
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else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
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else llvm_unreachable("unknown memory type");
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// Build indexed load.
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SDValue TargetConstOff = CurDAG->getTargetConstant(Offset, PointerTy);
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SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
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LD->getValueType(0),
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MVT::Other,
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SDValue(NewBase,0),
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TargetConstOff,
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Chain);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
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ReplaceUses(LD, Result);
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return Result;
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}
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}
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return SelectCode(LD);
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}
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SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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unsigned Opcode,
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SDLoc dl)
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{
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SDValue Chain = LD->getChain();
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EVT LoadedVT = LD->getMemoryVT();
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SDValue Base = LD->getBasePtr();
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SDValue Offset = LD->getOffset();
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SDNode *OffsetNode = Offset.getNode();
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int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
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SDValue N1 = LD->getOperand(1);
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SDValue CPTmpN1_0;
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SDValue CPTmpN1_1;
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if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
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N1.getNode()->getValueType(0) == MVT::i32) {
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const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
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if (TII->isValidAutoIncImm(LoadedVT, Val)) {
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SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
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SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
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MVT::Other, Base, TargetConst,
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Chain);
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SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
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SDValue(Result_1, 0));
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
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const SDValue Froms[] = { SDValue(LD, 0),
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SDValue(LD, 1),
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SDValue(LD, 2)
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};
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const SDValue Tos[] = { SDValue(Result_2, 0),
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SDValue(Result_1, 1),
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SDValue(Result_1, 2)
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};
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ReplaceUses(Froms, Tos, 3);
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return Result_2;
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}
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
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|
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
|
|
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
|
|
MVT::Other, Base, TargetConst0,
|
|
Chain);
|
|
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl,
|
|
MVT::i64, SDValue(Result_1, 0));
|
|
SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
|
|
MVT::i32, Base, TargetConstVal,
|
|
SDValue(Result_1, 1));
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
MemOp[0] = LD->getMemOperand();
|
|
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
|
|
const SDValue Froms[] = { SDValue(LD, 0),
|
|
SDValue(LD, 1),
|
|
SDValue(LD, 2)
|
|
};
|
|
const SDValue Tos[] = { SDValue(Result_2, 0),
|
|
SDValue(Result_3, 0),
|
|
SDValue(Result_1, 1)
|
|
};
|
|
ReplaceUses(Froms, Tos, 3);
|
|
return Result_2;
|
|
}
|
|
return SelectCode(LD);
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
|
|
unsigned Opcode,
|
|
SDLoc dl)
|
|
{
|
|
SDValue Chain = LD->getChain();
|
|
EVT LoadedVT = LD->getMemoryVT();
|
|
SDValue Base = LD->getBasePtr();
|
|
SDValue Offset = LD->getOffset();
|
|
SDNode *OffsetNode = Offset.getNode();
|
|
int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
|
|
SDValue N1 = LD->getOperand(1);
|
|
SDValue CPTmpN1_0;
|
|
SDValue CPTmpN1_1;
|
|
|
|
if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
|
|
N1.getNode()->getValueType(0) == MVT::i32) {
|
|
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
|
|
if (TII->isValidAutoIncImm(LoadedVT, Val)) {
|
|
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
|
|
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
|
|
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
|
|
MVT::i32, MVT::Other, Base,
|
|
TargetConstVal, Chain);
|
|
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
|
|
TargetConst0);
|
|
SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
|
|
MVT::i64, MVT::Other,
|
|
SDValue(Result_2,0),
|
|
SDValue(Result_1,0));
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
MemOp[0] = LD->getMemOperand();
|
|
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
|
|
const SDValue Froms[] = { SDValue(LD, 0),
|
|
SDValue(LD, 1),
|
|
SDValue(LD, 2)
|
|
};
|
|
const SDValue Tos[] = { SDValue(Result_3, 0),
|
|
SDValue(Result_1, 1),
|
|
SDValue(Result_1, 2)
|
|
};
|
|
ReplaceUses(Froms, Tos, 3);
|
|
return Result_3;
|
|
}
|
|
|
|
// Generate an indirect load.
|
|
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
|
|
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
|
|
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
|
|
MVT::Other,
|
|
Base, TargetConst0, Chain);
|
|
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
|
|
TargetConst0);
|
|
SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
|
|
MVT::i64, MVT::Other,
|
|
SDValue(Result_2,0),
|
|
SDValue(Result_1,0));
|
|
// Add offset to base.
|
|
SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
|
|
Base, TargetConstVal,
|
|
SDValue(Result_1, 1));
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
MemOp[0] = LD->getMemOperand();
|
|
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
|
|
const SDValue Froms[] = { SDValue(LD, 0),
|
|
SDValue(LD, 1),
|
|
SDValue(LD, 2)
|
|
};
|
|
const SDValue Tos[] = { SDValue(Result_3, 0), // Load value.
|
|
SDValue(Result_4, 0), // New address.
|
|
SDValue(Result_1, 1)
|
|
};
|
|
ReplaceUses(Froms, Tos, 3);
|
|
return Result_3;
|
|
}
|
|
|
|
return SelectCode(LD);
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
|
|
SDValue Chain = LD->getChain();
|
|
SDValue Base = LD->getBasePtr();
|
|
SDValue Offset = LD->getOffset();
|
|
SDNode *OffsetNode = Offset.getNode();
|
|
// Get the constant value.
|
|
int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
|
|
EVT LoadedVT = LD->getMemoryVT();
|
|
unsigned Opcode = 0;
|
|
|
|
// Check for zero ext loads.
|
|
bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
|
|
|
|
// Figure out the opcode.
|
|
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
|
|
if (LoadedVT == MVT::i64) {
|
|
if (TII->isValidAutoIncImm(LoadedVT, Val))
|
|
Opcode = Hexagon::L2_loadrd_pi;
|
|
else
|
|
Opcode = Hexagon::L2_loadrd_io;
|
|
} else if (LoadedVT == MVT::i32) {
|
|
if (TII->isValidAutoIncImm(LoadedVT, Val))
|
|
Opcode = Hexagon::L2_loadri_pi;
|
|
else
|
|
Opcode = Hexagon::L2_loadri_io;
|
|
} else if (LoadedVT == MVT::i16) {
|
|
if (TII->isValidAutoIncImm(LoadedVT, Val))
|
|
Opcode = zextval ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
|
|
else
|
|
Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
|
|
} else if (LoadedVT == MVT::i8) {
|
|
if (TII->isValidAutoIncImm(LoadedVT, Val))
|
|
Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
|
|
else
|
|
Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
|
|
} else
|
|
llvm_unreachable("unknown memory type");
|
|
|
|
// For zero ext i64 loads, we need to add combine instructions.
|
|
if (LD->getValueType(0) == MVT::i64 &&
|
|
LD->getExtensionType() == ISD::ZEXTLOAD) {
|
|
return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
|
|
}
|
|
if (LD->getValueType(0) == MVT::i64 &&
|
|
LD->getExtensionType() == ISD::SEXTLOAD) {
|
|
// Handle sign ext i64 loads.
|
|
return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
|
|
}
|
|
if (TII->isValidAutoIncImm(LoadedVT, Val)) {
|
|
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
|
|
SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
|
|
LD->getValueType(0),
|
|
MVT::i32, MVT::Other, Base,
|
|
TargetConstVal, Chain);
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
MemOp[0] = LD->getMemOperand();
|
|
cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
|
|
const SDValue Froms[] = { SDValue(LD, 0),
|
|
SDValue(LD, 1),
|
|
SDValue(LD, 2)
|
|
};
|
|
const SDValue Tos[] = { SDValue(Result, 0),
|
|
SDValue(Result, 1),
|
|
SDValue(Result, 2)
|
|
};
|
|
ReplaceUses(Froms, Tos, 3);
|
|
return Result;
|
|
} else {
|
|
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
|
|
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
|
|
SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
|
|
LD->getValueType(0),
|
|
MVT::Other, Base, TargetConst0,
|
|
Chain);
|
|
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
|
|
Base, TargetConstVal,
|
|
SDValue(Result_1, 1));
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
MemOp[0] = LD->getMemOperand();
|
|
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
|
|
const SDValue Froms[] = { SDValue(LD, 0),
|
|
SDValue(LD, 1),
|
|
SDValue(LD, 2)
|
|
};
|
|
const SDValue Tos[] = { SDValue(Result_1, 0),
|
|
SDValue(Result_2, 0),
|
|
SDValue(Result_1, 1)
|
|
};
|
|
ReplaceUses(Froms, Tos, 3);
|
|
return Result_1;
|
|
}
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
|
|
SDNode *result;
|
|
SDLoc dl(N);
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
ISD::MemIndexedMode AM = LD->getAddressingMode();
|
|
|
|
// Handle indexed loads.
|
|
if (AM != ISD::UNINDEXED) {
|
|
result = SelectIndexedLoad(LD, dl);
|
|
} else {
|
|
result = SelectBaseOffsetLoad(LD, dl);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
|
|
SDValue Chain = ST->getChain();
|
|
SDValue Base = ST->getBasePtr();
|
|
SDValue Offset = ST->getOffset();
|
|
SDValue Value = ST->getValue();
|
|
SDNode *OffsetNode = Offset.getNode();
|
|
// Get the constant value.
|
|
int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
|
|
EVT StoredVT = ST->getMemoryVT();
|
|
|
|
// Offset value must be within representable range
|
|
// and must have correct alignment properties.
|
|
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
|
|
if (TII->isValidAutoIncImm(StoredVT, Val)) {
|
|
SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
|
|
Chain};
|
|
unsigned Opcode = 0;
|
|
|
|
// Figure out the post inc version of opcode.
|
|
if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
|
|
else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
|
|
else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
|
|
else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
|
|
else llvm_unreachable("unknown memory type");
|
|
|
|
// Build post increment store.
|
|
SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
|
|
MVT::Other, Ops);
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
MemOp[0] = ST->getMemOperand();
|
|
cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
|
|
|
|
ReplaceUses(ST, Result);
|
|
ReplaceUses(SDValue(ST,1), SDValue(Result,1));
|
|
return Result;
|
|
}
|
|
|
|
// Note: Order of operands matches the def of instruction:
|
|
// def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ...
|
|
// and it differs for POST_ST* for instance.
|
|
SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
|
|
Chain};
|
|
unsigned Opcode = 0;
|
|
|
|
// Figure out the opcode.
|
|
if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
|
|
else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
|
|
else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
|
|
else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
|
|
else llvm_unreachable("unknown memory type");
|
|
|
|
// Build regular store.
|
|
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
|
|
SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
|
|
// Build splitted incriment instruction.
|
|
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
|
|
Base,
|
|
TargetConstVal,
|
|
SDValue(Result_1, 0));
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
MemOp[0] = ST->getMemOperand();
|
|
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
|
|
|
|
ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
|
|
ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
|
|
return Result_2;
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectBaseOffsetStore(StoreSDNode *ST,
|
|
SDLoc dl) {
|
|
SDValue Chain = ST->getChain();
|
|
SDNode* Const32 = ST->getBasePtr().getNode();
|
|
SDValue Value = ST->getValue();
|
|
unsigned Opcode = 0;
|
|
|
|
// Try to lower stores of GlobalAdresses into indexed stores. Custom
|
|
// lowering for GlobalAddress nodes has already turned it into a
|
|
// CONST32. Avoid truncating stores for the moment. Post-inc stores
|
|
// do the same. Don't think there's a reason for it, so will file a
|
|
// bug to fix.
|
|
if ((Const32->getOpcode() == HexagonISD::CONST32) &&
|
|
!(Value.getValueType() == MVT::i64 && ST->isTruncatingStore())) {
|
|
SDValue Base = Const32->getOperand(0);
|
|
if (Base.getOpcode() == ISD::TargetGlobalAddress) {
|
|
EVT StoredVT = ST->getMemoryVT();
|
|
int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
|
|
if (Offset != 0 && OffsetFitsS11(StoredVT, Offset)) {
|
|
MVT PointerTy = getTargetLowering()->getPointerTy();
|
|
const GlobalValue* GV =
|
|
cast<GlobalAddressSDNode>(Base)->getGlobal();
|
|
SDValue TargAddr =
|
|
CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
|
|
SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
|
|
dl, PointerTy,
|
|
TargAddr);
|
|
|
|
// Figure out base + offset opcode
|
|
if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
|
|
else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
|
|
else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
|
|
else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
|
|
else llvm_unreachable("unknown memory type");
|
|
|
|
SDValue Ops[] = {SDValue(NewBase,0),
|
|
CurDAG->getTargetConstant(Offset,PointerTy),
|
|
Value, Chain};
|
|
// build indexed store
|
|
SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
|
|
MVT::Other, Ops);
|
|
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
|
MemOp[0] = ST->getMemOperand();
|
|
cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
|
|
ReplaceUses(ST, Result);
|
|
return Result;
|
|
}
|
|
}
|
|
}
|
|
|
|
return SelectCode(ST);
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
|
|
SDLoc dl(N);
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
// Handle indexed stores.
|
|
if (AM != ISD::UNINDEXED) {
|
|
return SelectIndexedStore(ST, dl);
|
|
}
|
|
|
|
return SelectBaseOffsetStore(ST, dl);
|
|
}
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
|
|
SDLoc dl(N);
|
|
|
|
//
|
|
// %conv.i = sext i32 %tmp1 to i64
|
|
// %conv2.i = sext i32 %add to i64
|
|
// %mul.i = mul nsw i64 %conv2.i, %conv.i
|
|
//
|
|
// --- match with the following ---
|
|
//
|
|
// %mul.i = mpy (%tmp1, %add)
|
|
//
|
|
|
|
if (N->getValueType(0) == MVT::i64) {
|
|
// Shifting a i64 signed multiply.
|
|
SDValue MulOp0 = N->getOperand(0);
|
|
SDValue MulOp1 = N->getOperand(1);
|
|
|
|
SDValue OP0;
|
|
SDValue OP1;
|
|
|
|
// Handle sign_extend and sextload.
|
|
if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
|
|
SDValue Sext0 = MulOp0.getOperand(0);
|
|
if (Sext0.getNode()->getValueType(0) != MVT::i32) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
OP0 = Sext0;
|
|
} else if (MulOp0.getOpcode() == ISD::LOAD) {
|
|
LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
|
|
if (LD->getMemoryVT() != MVT::i32 ||
|
|
LD->getExtensionType() != ISD::SEXTLOAD ||
|
|
LD->getAddressingMode() != ISD::UNINDEXED) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
SDValue Chain = LD->getChain();
|
|
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
|
|
OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
|
|
MVT::Other,
|
|
LD->getBasePtr(), TargetConst0,
|
|
Chain), 0);
|
|
} else {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
// Same goes for the second operand.
|
|
if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
|
|
SDValue Sext1 = MulOp1.getOperand(0);
|
|
if (Sext1.getNode()->getValueType(0) != MVT::i32) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
OP1 = Sext1;
|
|
} else if (MulOp1.getOpcode() == ISD::LOAD) {
|
|
LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
|
|
if (LD->getMemoryVT() != MVT::i32 ||
|
|
LD->getExtensionType() != ISD::SEXTLOAD ||
|
|
LD->getAddressingMode() != ISD::UNINDEXED) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
SDValue Chain = LD->getChain();
|
|
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
|
|
OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
|
|
MVT::Other,
|
|
LD->getBasePtr(), TargetConst0,
|
|
Chain), 0);
|
|
} else {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
// Generate a mpy instruction.
|
|
SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
|
|
OP0, OP1);
|
|
ReplaceUses(N, Result);
|
|
return Result;
|
|
}
|
|
|
|
return SelectCode(N);
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
|
|
SDLoc dl(N);
|
|
SDValue N0 = N->getOperand(0);
|
|
if (N0.getOpcode() == ISD::SETCC) {
|
|
SDValue N00 = N0.getOperand(0);
|
|
if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
|
|
SDValue N000 = N00.getOperand(0);
|
|
SDValue N001 = N00.getOperand(1);
|
|
if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
|
|
SDValue N01 = N0.getOperand(1);
|
|
SDValue N02 = N0.getOperand(2);
|
|
|
|
// Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
|
|
// i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
|
|
// IntRegs:i32:$src2)
|
|
// Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
|
|
// Pattern complexity = 9 cost = 1 size = 0.
|
|
if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
|
|
SDValue N1 = N->getOperand(1);
|
|
if (N01 == N1) {
|
|
SDValue N2 = N->getOperand(2);
|
|
if (N000 == N2 &&
|
|
N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
|
|
N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
|
|
SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
|
|
MVT::i32, N000);
|
|
SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_max, dl,
|
|
MVT::i32,
|
|
SDValue(SextNode, 0),
|
|
N1);
|
|
ReplaceUses(N, Result);
|
|
return Result;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
|
|
// i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
|
|
// IntRegs:i32:$src2)
|
|
// Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
|
|
// Pattern complexity = 9 cost = 1 size = 0.
|
|
if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
|
|
SDValue N1 = N->getOperand(1);
|
|
if (N01 == N1) {
|
|
SDValue N2 = N->getOperand(2);
|
|
if (N000 == N2 &&
|
|
N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
|
|
N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
|
|
SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
|
|
MVT::i32, N000);
|
|
SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_min, dl,
|
|
MVT::i32,
|
|
SDValue(SextNode, 0),
|
|
N1);
|
|
ReplaceUses(N, Result);
|
|
return Result;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return SelectCode(N);
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
|
|
SDLoc dl(N);
|
|
SDValue Shift = N->getOperand(0);
|
|
|
|
//
|
|
// %conv.i = sext i32 %tmp1 to i64
|
|
// %conv2.i = sext i32 %add to i64
|
|
// %mul.i = mul nsw i64 %conv2.i, %conv.i
|
|
// %shr5.i = lshr i64 %mul.i, 32
|
|
// %conv3.i = trunc i64 %shr5.i to i32
|
|
//
|
|
// --- match with the following ---
|
|
//
|
|
// %conv3.i = mpy (%tmp1, %add)
|
|
//
|
|
// Trunc to i32.
|
|
if (N->getValueType(0) == MVT::i32) {
|
|
// Trunc from i64.
|
|
if (Shift.getNode()->getValueType(0) == MVT::i64) {
|
|
// Trunc child is logical shift right.
|
|
if (Shift.getOpcode() != ISD::SRL) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
SDValue ShiftOp0 = Shift.getOperand(0);
|
|
SDValue ShiftOp1 = Shift.getOperand(1);
|
|
|
|
// Shift by const 32
|
|
if (ShiftOp1.getOpcode() != ISD::Constant) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
int32_t ShiftConst =
|
|
cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
|
|
if (ShiftConst != 32) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
// Shifting a i64 signed multiply
|
|
SDValue Mul = ShiftOp0;
|
|
if (Mul.getOpcode() != ISD::MUL) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
SDValue MulOp0 = Mul.getOperand(0);
|
|
SDValue MulOp1 = Mul.getOperand(1);
|
|
|
|
SDValue OP0;
|
|
SDValue OP1;
|
|
|
|
// Handle sign_extend and sextload
|
|
if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
|
|
SDValue Sext0 = MulOp0.getOperand(0);
|
|
if (Sext0.getNode()->getValueType(0) != MVT::i32) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
OP0 = Sext0;
|
|
} else if (MulOp0.getOpcode() == ISD::LOAD) {
|
|
LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
|
|
if (LD->getMemoryVT() != MVT::i32 ||
|
|
LD->getExtensionType() != ISD::SEXTLOAD ||
|
|
LD->getAddressingMode() != ISD::UNINDEXED) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
SDValue Chain = LD->getChain();
|
|
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
|
|
OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
|
|
MVT::Other,
|
|
LD->getBasePtr(),
|
|
TargetConst0, Chain), 0);
|
|
} else {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
// Same goes for the second operand.
|
|
if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
|
|
SDValue Sext1 = MulOp1.getOperand(0);
|
|
if (Sext1.getNode()->getValueType(0) != MVT::i32)
|
|
return SelectCode(N);
|
|
|
|
OP1 = Sext1;
|
|
} else if (MulOp1.getOpcode() == ISD::LOAD) {
|
|
LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
|
|
if (LD->getMemoryVT() != MVT::i32 ||
|
|
LD->getExtensionType() != ISD::SEXTLOAD ||
|
|
LD->getAddressingMode() != ISD::UNINDEXED) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
SDValue Chain = LD->getChain();
|
|
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
|
|
OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
|
|
MVT::Other,
|
|
LD->getBasePtr(),
|
|
TargetConst0, Chain), 0);
|
|
} else {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
// Generate a mpy instruction.
|
|
SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpy_up, dl, MVT::i32,
|
|
OP0, OP1);
|
|
ReplaceUses(N, Result);
|
|
return Result;
|
|
}
|
|
}
|
|
|
|
return SelectCode(N);
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
|
|
SDLoc dl(N);
|
|
if (N->getValueType(0) == MVT::i32) {
|
|
SDValue Shl_0 = N->getOperand(0);
|
|
SDValue Shl_1 = N->getOperand(1);
|
|
// RHS is const.
|
|
if (Shl_1.getOpcode() == ISD::Constant) {
|
|
if (Shl_0.getOpcode() == ISD::MUL) {
|
|
SDValue Mul_0 = Shl_0.getOperand(0); // Val
|
|
SDValue Mul_1 = Shl_0.getOperand(1); // Const
|
|
// RHS of mul is const.
|
|
if (Mul_1.getOpcode() == ISD::Constant) {
|
|
int32_t ShlConst =
|
|
cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
|
|
int32_t MulConst =
|
|
cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
|
|
int32_t ValConst = MulConst << ShlConst;
|
|
SDValue Val = CurDAG->getTargetConstant(ValConst,
|
|
MVT::i32);
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
|
|
if (isInt<9>(CN->getSExtValue())) {
|
|
SDNode* Result =
|
|
CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
|
|
MVT::i32, Mul_0, Val);
|
|
ReplaceUses(N, Result);
|
|
return Result;
|
|
}
|
|
|
|
}
|
|
} else if (Shl_0.getOpcode() == ISD::SUB) {
|
|
SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
|
|
SDValue Sub_1 = Shl_0.getOperand(1); // Val
|
|
if (Sub_0.getOpcode() == ISD::Constant) {
|
|
int32_t SubConst =
|
|
cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
|
|
if (SubConst == 0) {
|
|
if (Sub_1.getOpcode() == ISD::SHL) {
|
|
SDValue Shl2_0 = Sub_1.getOperand(0); // Val
|
|
SDValue Shl2_1 = Sub_1.getOperand(1); // Const
|
|
if (Shl2_1.getOpcode() == ISD::Constant) {
|
|
int32_t ShlConst =
|
|
cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
|
|
int32_t Shl2Const =
|
|
cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
|
|
int32_t ValConst = 1 << (ShlConst+Shl2Const);
|
|
SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
|
|
if (ConstantSDNode *CN =
|
|
dyn_cast<ConstantSDNode>(Val.getNode()))
|
|
if (isInt<9>(CN->getSExtValue())) {
|
|
SDNode* Result =
|
|
CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
|
|
Shl2_0, Val);
|
|
ReplaceUses(N, Result);
|
|
return Result;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return SelectCode(N);
|
|
}
|
|
|
|
|
|
//
|
|
// If there is an zero_extend followed an intrinsic in DAG (this means - the
|
|
// result of the intrinsic is predicate); convert the zero_extend to
|
|
// transfer instruction.
|
|
//
|
|
// Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
|
|
// converted into a MUX as predicate registers defined as 1 bit in the
|
|
// compiler. Architecture defines them as 8-bit registers.
|
|
// We want to preserve all the lower 8-bits and, not just 1 LSB bit.
|
|
//
|
|
SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
|
|
SDLoc dl(N);
|
|
SDNode *IsIntrinsic = N->getOperand(0).getNode();
|
|
if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
|
|
unsigned ID =
|
|
cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
|
|
if (doesIntrinsicReturnPredicate(ID)) {
|
|
// Now we need to differentiate target data types.
|
|
if (N->getValueType(0) == MVT::i64) {
|
|
// Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs).
|
|
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
|
|
SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
|
|
MVT::i32,
|
|
SDValue(IsIntrinsic, 0));
|
|
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
|
|
MVT::i32,
|
|
TargetConst0);
|
|
SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
|
|
MVT::i64, MVT::Other,
|
|
SDValue(Result_2, 0),
|
|
SDValue(Result_1, 0));
|
|
ReplaceUses(N, Result_3);
|
|
return Result_3;
|
|
}
|
|
if (N->getValueType(0) == MVT::i32) {
|
|
// Convert the zero_extend to Rs = Pd
|
|
SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
|
|
MVT::i32,
|
|
SDValue(IsIntrinsic, 0));
|
|
ReplaceUses(N, RsPd);
|
|
return RsPd;
|
|
}
|
|
llvm_unreachable("Unexpected value type");
|
|
}
|
|
}
|
|
return SelectCode(N);
|
|
}
|
|
|
|
//
|
|
// Checking for intrinsics which have predicate registers as operand(s)
|
|
// and lowering to the actual intrinsic.
|
|
//
|
|
SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
|
|
unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
|
|
unsigned Bits;
|
|
switch (IID) {
|
|
case Intrinsic::hexagon_S2_vsplatrb:
|
|
Bits = 8;
|
|
break;
|
|
case Intrinsic::hexagon_S2_vsplatrh:
|
|
Bits = 16;
|
|
break;
|
|
default:
|
|
return SelectCode(N);
|
|
}
|
|
|
|
SDValue const &V = N->getOperand(1);
|
|
SDValue U;
|
|
if (isValueExtension(V, Bits, U)) {
|
|
SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
|
|
N->getOperand(0), U);
|
|
return SelectCode(R.getNode());
|
|
}
|
|
return SelectCode(N);
|
|
}
|
|
|
|
//
|
|
// Map floating point constant values.
|
|
//
|
|
SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
|
|
SDLoc dl(N);
|
|
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
|
|
APFloat APF = CN->getValueAPF();
|
|
if (N->getValueType(0) == MVT::f32) {
|
|
return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
|
|
CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
|
|
}
|
|
else if (N->getValueType(0) == MVT::f64) {
|
|
return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
|
|
CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
|
|
}
|
|
|
|
return SelectCode(N);
|
|
}
|
|
|
|
|
|
//
|
|
// Map predicate true (encoded as -1 in LLVM) to a XOR.
|
|
//
|
|
SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
|
|
SDLoc dl(N);
|
|
if (N->getValueType(0) == MVT::i1) {
|
|
SDNode* Result;
|
|
int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
|
|
if (Val == -1) {
|
|
// Create the IntReg = 1 node.
|
|
SDNode* IntRegTFR =
|
|
CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
|
|
CurDAG->getTargetConstant(0, MVT::i32));
|
|
|
|
// Pd = IntReg
|
|
SDNode* Pd = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
|
|
SDValue(IntRegTFR, 0));
|
|
|
|
// not(Pd)
|
|
SDNode* NotPd = CurDAG->getMachineNode(Hexagon::C2_not, dl, MVT::i1,
|
|
SDValue(Pd, 0));
|
|
|
|
// xor(not(Pd))
|
|
Result = CurDAG->getMachineNode(Hexagon::C2_xor, dl, MVT::i1,
|
|
SDValue(Pd, 0), SDValue(NotPd, 0));
|
|
|
|
// We have just built:
|
|
// Rs = Pd
|
|
// Pd = xor(not(Pd), Pd)
|
|
|
|
ReplaceUses(N, Result);
|
|
return Result;
|
|
}
|
|
}
|
|
|
|
return SelectCode(N);
|
|
}
|
|
|
|
|
|
//
|
|
// Map add followed by a asr -> asr +=.
|
|
//
|
|
SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
|
|
SDLoc dl(N);
|
|
if (N->getValueType(0) != MVT::i32) {
|
|
return SelectCode(N);
|
|
}
|
|
// Identify nodes of the form: add(asr(...)).
|
|
SDNode* Src1 = N->getOperand(0).getNode();
|
|
if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
|
|
|| Src1->getValueType(0) != MVT::i32) {
|
|
return SelectCode(N);
|
|
}
|
|
|
|
// Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
|
|
// Rd and Rd' are assigned to the same register
|
|
SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
|
|
N->getOperand(1),
|
|
Src1->getOperand(0),
|
|
Src1->getOperand(1));
|
|
ReplaceUses(N, Result);
|
|
|
|
return Result;
|
|
}
|
|
|
|
|
|
SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
|
|
if (N->isMachineOpcode()) {
|
|
N->setNodeId(-1);
|
|
return nullptr; // Already selected.
|
|
}
|
|
|
|
|
|
switch (N->getOpcode()) {
|
|
case ISD::Constant:
|
|
return SelectConstant(N);
|
|
|
|
case ISD::ConstantFP:
|
|
return SelectConstantFP(N);
|
|
|
|
case ISD::ADD:
|
|
return SelectAdd(N);
|
|
|
|
case ISD::SHL:
|
|
return SelectSHL(N);
|
|
|
|
case ISD::LOAD:
|
|
return SelectLoad(N);
|
|
|
|
case ISD::STORE:
|
|
return SelectStore(N);
|
|
|
|
case ISD::SELECT:
|
|
return SelectSelect(N);
|
|
|
|
case ISD::TRUNCATE:
|
|
return SelectTruncate(N);
|
|
|
|
case ISD::MUL:
|
|
return SelectMul(N);
|
|
|
|
case ISD::ZERO_EXTEND:
|
|
return SelectZeroExtend(N);
|
|
|
|
case ISD::INTRINSIC_WO_CHAIN:
|
|
return SelectIntrinsicWOChain(N);
|
|
}
|
|
|
|
return SelectCode(N);
|
|
}
|
|
|
|
|
|
//
|
|
// Hexagon_TODO: Five functions for ADDRri?! Surely there must be a better way
|
|
// to define these instructions.
|
|
//
|
|
bool HexagonDAGToDAGISel::SelectADDRri(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::SelectADDRriS11_0(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsS11_0_Offset(Offset.getNode()));
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsS11_0_Offset(Offset.getNode()));
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::SelectADDRriS11_1(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsS11_1_Offset(Offset.getNode()));
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsS11_1_Offset(Offset.getNode()));
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::SelectADDRriS11_2(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsS11_2_Offset(Offset.getNode()));
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsS11_2_Offset(Offset.getNode()));
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::SelectADDRriU6_0(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsU6_0_Offset(Offset.getNode()));
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsU6_0_Offset(Offset.getNode()));
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::SelectADDRriU6_1(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsU6_1_Offset(Offset.getNode()));
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsU6_1_Offset(Offset.getNode()));
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::SelectADDRriU6_2(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsU6_2_Offset(Offset.getNode()));
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsU6_2_Offset(Offset.getNode()));
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::SelectMEMriS11_2(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
|
|
if (Addr.getOpcode() != ISD::ADD) {
|
|
return(SelectADDRriS11_2(Addr, Base, Offset));
|
|
}
|
|
|
|
return SelectADDRriS11_2(Addr, Base, Offset);
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::SelectADDRriS11_3(SDValue& Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsS11_3_Offset(Offset.getNode()));
|
|
}
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return (IsS11_3_Offset(Offset.getNode()));
|
|
}
|
|
|
|
bool HexagonDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1,
|
|
SDValue &R2) {
|
|
if (Addr.getOpcode() == ISD::FrameIndex) return false;
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
|
|
if (isInt<13>(CN->getSExtValue()))
|
|
return false; // Let the reg+imm pattern catch this!
|
|
R1 = Addr.getOperand(0);
|
|
R2 = Addr.getOperand(1);
|
|
return true;
|
|
}
|
|
|
|
R1 = Addr;
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
// Handle generic address case. It is accessed from inlined asm =m constraints,
|
|
// which could have any kind of pointer.
|
|
bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
|
|
SDValue &Base, SDValue &Offset) {
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // Direct calls.
|
|
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
Base = Addr.getOperand(0);
|
|
Offset = Addr.getOperand(1);
|
|
return true;
|
|
}
|
|
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
|
|
bool HexagonDAGToDAGISel::
|
|
SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
|
|
std::vector<SDValue> &OutOps) {
|
|
SDValue Op0, Op1;
|
|
|
|
switch (ConstraintCode) {
|
|
case 'o': // Offsetable.
|
|
case 'v': // Not offsetable.
|
|
default: return true;
|
|
case 'm': // Memory.
|
|
if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
|
|
return true;
|
|
break;
|
|
}
|
|
|
|
OutOps.push_back(Op0);
|
|
OutOps.push_back(Op1);
|
|
return false;
|
|
}
|
|
|
|
bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
|
|
unsigned UseCount = 0;
|
|
for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
|
|
UseCount++;
|
|
}
|
|
|
|
return (UseCount <= 1);
|
|
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Return 'true' if use count of the global address is below threshold.
|
|
//===--------------------------------------------------------------------===//
|
|
bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
|
|
assert(N->getOpcode() == ISD::TargetGlobalAddress &&
|
|
"Expecting a target global address");
|
|
|
|
// Always try to fold the address.
|
|
if (TM.getOptLevel() == CodeGenOpt::Aggressive)
|
|
return true;
|
|
|
|
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
|
|
DenseMap<const GlobalValue *, unsigned>::const_iterator GI =
|
|
GlobalAddressUseCountMap.find(GA->getGlobal());
|
|
|
|
if (GI == GlobalAddressUseCountMap.end())
|
|
return false;
|
|
|
|
return GI->second <= MaxNumOfUsesForConstExtenders;
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Return true if the non-GP-relative global address can be folded.
|
|
//===--------------------------------------------------------------------===//
|
|
inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
|
|
return foldGlobalAddressImpl(N, R, false);
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Return true if the GP-relative global address can be folded.
|
|
//===--------------------------------------------------------------------===//
|
|
inline bool HexagonDAGToDAGISel::foldGlobalAddressGP(SDValue &N, SDValue &R) {
|
|
return foldGlobalAddressImpl(N, R, true);
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Fold offset of the global address if number of uses are below threshold.
|
|
//===--------------------------------------------------------------------===//
|
|
bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
|
|
bool ShouldLookForGP) {
|
|
if (N.getOpcode() == ISD::ADD) {
|
|
SDValue N0 = N.getOperand(0);
|
|
SDValue N1 = N.getOperand(1);
|
|
if ((ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32_GP)) ||
|
|
(!ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32))) {
|
|
ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1);
|
|
GlobalAddressSDNode *GA =
|
|
dyn_cast<GlobalAddressSDNode>(N0.getOperand(0));
|
|
|
|
if (Const && GA &&
|
|
(GA->getOpcode() == ISD::TargetGlobalAddress)) {
|
|
if ((N0.getOpcode() == HexagonISD::CONST32) &&
|
|
!hasNumUsesBelowThresGA(GA))
|
|
return false;
|
|
R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
|
|
SDLoc(Const),
|
|
N.getValueType(),
|
|
GA->getOffset() +
|
|
(uint64_t)Const->getSExtValue());
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
|
|
if (N.getOpcode() != ISD::FrameIndex)
|
|
return false;
|
|
FrameIndexSDNode *FX = cast<FrameIndexSDNode>(N);
|
|
R = CurDAG->getTargetFrameIndex(FX->getIndex(), MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
|
|
return SelectGlobalAddress(N, R, false);
|
|
}
|
|
|
|
inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
|
|
return SelectGlobalAddress(N, R, true);
|
|
}
|
|
|
|
bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
|
|
bool UseGP) {
|
|
switch (N.getOpcode()) {
|
|
case ISD::ADD: {
|
|
SDValue N0 = N.getOperand(0);
|
|
SDValue N1 = N.getOperand(1);
|
|
unsigned GAOpc = N0.getOpcode();
|
|
if (UseGP && GAOpc != HexagonISD::CONST32_GP)
|
|
return false;
|
|
if (!UseGP && GAOpc != HexagonISD::CONST32)
|
|
return false;
|
|
if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
|
|
SDValue Addr = N0.getOperand(0);
|
|
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
|
|
if (GA->getOpcode() == ISD::TargetGlobalAddress) {
|
|
uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
|
|
R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
|
|
N.getValueType(), NewOff);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case HexagonISD::CONST32:
|
|
// The operand(0) of CONST32 is TargetGlobalAddress, which is what we
|
|
// want in the instruction.
|
|
if (!UseGP)
|
|
R = N.getOperand(0);
|
|
return !UseGP;
|
|
case HexagonISD::CONST32_GP:
|
|
if (UseGP)
|
|
R = N.getOperand(0);
|
|
return UseGP;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool HexagonDAGToDAGISel::isValueExtension(SDValue const &Val,
|
|
unsigned FromBits, SDValue &Src) {
|
|
unsigned Opc = Val.getOpcode();
|
|
switch (Opc) {
|
|
case ISD::SIGN_EXTEND:
|
|
case ISD::ZERO_EXTEND:
|
|
case ISD::ANY_EXTEND: {
|
|
SDValue const &Op0 = Val.getOperand(0);
|
|
EVT T = Op0.getValueType();
|
|
if (T.isInteger() && T.getSizeInBits() == FromBits) {
|
|
Src = Op0;
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
case ISD::SIGN_EXTEND_INREG:
|
|
case ISD::AssertSext:
|
|
case ISD::AssertZext:
|
|
if (Val.getOperand(0).getValueType().isInteger()) {
|
|
VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
|
|
if (T->getVT().getSizeInBits() == FromBits) {
|
|
Src = Val.getOperand(0);
|
|
return true;
|
|
}
|
|
}
|
|
break;
|
|
case ISD::AND: {
|
|
// Check if this is an AND with "FromBits" of lower bits set to 1.
|
|
uint64_t FromMask = (1 << FromBits) - 1;
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
|
|
if (C->getZExtValue() == FromMask) {
|
|
Src = Val.getOperand(1);
|
|
return true;
|
|
}
|
|
}
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
|
|
if (C->getZExtValue() == FromMask) {
|
|
Src = Val.getOperand(0);
|
|
return true;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case ISD::OR:
|
|
case ISD::XOR: {
|
|
// OR/XOR with the lower "FromBits" bits set to 0.
|
|
uint64_t FromMask = (1 << FromBits) - 1;
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
|
|
if ((C->getZExtValue() & FromMask) == 0) {
|
|
Src = Val.getOperand(1);
|
|
return true;
|
|
}
|
|
}
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
|
|
if ((C->getZExtValue() & FromMask) == 0) {
|
|
Src = Val.getOperand(0);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
return false;
|
|
}
|