mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-03 08:55:51 +00:00
4403b930f8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8
535 lines
15 KiB
TableGen
535 lines
15 KiB
TableGen
//===- SystemZInstrFormats.td - SystemZ Instruction Formats ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class InstSystemZ<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
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let Namespace = "SystemZ";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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//===----------------------------------------------------------------------===//
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// E format
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//===----------------------------------------------------------------------===//
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class F_E<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<16> Inst;
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let Inst{15-0} = opcode;
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}
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//===----------------------------------------------------------------------===//
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// I format
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//===----------------------------------------------------------------------===//
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class F_I<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-32} = opcode;
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//let Inst{31-0} = simm32;
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}
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//===----------------------------------------------------------------------===//
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// RR format
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//===----------------------------------------------------------------------===//
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class F_RR<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<16> Inst;
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let Inst{15-8} = opcode;
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}
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//===----------------------------------------------------------------------===//
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// RRE format
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//===----------------------------------------------------------------------===//
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class F_RRE<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-16} = opcode;
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let Inst{15-8} = 0;
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//let Inst{7-4} = r1;
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//let Inst{3-0} = r2;
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}
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//===----------------------------------------------------------------------===//
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// RRF format (1)
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//===----------------------------------------------------------------------===//
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class F_RRF_1<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-16} = opcode;
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//let Inst{15-12} = r1;
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let Inst{11-8} = 0;
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//let Inst{7-4} = r3;
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//let Inst{3-0} = r2;
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}
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//===----------------------------------------------------------------------===//
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// RRF format (2)
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//===----------------------------------------------------------------------===//
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class F_RRF_2<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-16} = opcode;
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//let Inst{15-12} = m3;
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let Inst{11-8} = 0;
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//let Inst{7-4} = r1;
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//let Inst{3-0} = r2;
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}
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//===----------------------------------------------------------------------===//
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// RRF format (3)
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//===----------------------------------------------------------------------===//
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class F_RRF_3<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-16} = opcode;
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//let Inst{15-12} = r3;
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//let Inst{11-8} = m4;
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//let Inst{7-4} = r1;
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//let Inst{3-0} = r2;
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}
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//===----------------------------------------------------------------------===//
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// RX format
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//===----------------------------------------------------------------------===//
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class F_RX<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = x2;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// RXE format
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//===----------------------------------------------------------------------===//
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class F_RXE<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = x2;
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//let Inst{31-28} = b2;
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//let Inst{27-16} = udisp12;
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let Inst{15-8} = 0;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RXF format
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//===----------------------------------------------------------------------===//
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class F_RXF<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r3;
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//let Inst{35-32} = x2;
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//let Inst{31-28} = b2;
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//let Inst{27-16} = udisp12;
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//let Inst{15-11} = r1;
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let Inst{11-8} = 0;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RXY format
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//===----------------------------------------------------------------------===//
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class F_RXY<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = x2;
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//let Inst{31-28} = b2;
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//let Inst{27-8} = sdisp20;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RS format (1)
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//===----------------------------------------------------------------------===//
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class F_RS_1<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = r3;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// RS format (2)
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//===----------------------------------------------------------------------===//
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class F_RS_2<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = m3;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// RS format (3)
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//===----------------------------------------------------------------------===//
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class F_RS_3<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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let Inst{19-16} = 0;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// RSY format (1)
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//===----------------------------------------------------------------------===//
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class F_RSY_1<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = r3;
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//let Inst{31-28} = b2;
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//let Inst{27-8} = sdisp20;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RSY format (2)
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//===----------------------------------------------------------------------===//
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class F_RSY_2<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = m3;
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//let Inst{31-28} = b2;
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//let Inst{27-8} = sdisp20;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RSL format
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//===----------------------------------------------------------------------===//
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class F_RSL<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = ll;
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let Inst{35-32} = 0;
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//let Inst{31-28} = b1;
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//let Inst{27-16} = udisp12;
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let Inst{15-8} = 0;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RSI format
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//===----------------------------------------------------------------------===//
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class F_RSI<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = r3;
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//let Inst{15-0} = simm16;
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}
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//===----------------------------------------------------------------------===//
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// RI format
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//===----------------------------------------------------------------------===//
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class F_RI<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-20} = r1;
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//let Inst{19-16} = op2;
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//let Inst{15-0} = simm16;
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}
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//===----------------------------------------------------------------------===//
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// RIE format
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//===----------------------------------------------------------------------===//
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class F_RIE<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = r2;
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//let Inst{31-16} = simm16;
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let Inst{15-8} = 0;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// RIL format (1)
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//===----------------------------------------------------------------------===//
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class F_RIL_1<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = op2;
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//let Inst{31-0} = simm32;
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}
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//===----------------------------------------------------------------------===//
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// RIL format (2)
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//===----------------------------------------------------------------------===//
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class F_RIL_2<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = m1;
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//let Inst{35-32} = op2;
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//let Inst{31-0} = simm32;
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}
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//===----------------------------------------------------------------------===//
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// SI format
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//===----------------------------------------------------------------------===//
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class F_SI<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-24} = opcode;
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//let Inst{23-16} = simm8;
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//let Inst{15-12} = b1;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// SIY format
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//===----------------------------------------------------------------------===//
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class F_SIY<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-32} = simm8;
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//let Inst{31-28} = b1;
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//let Inst{27-8} = sdisp20;
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//let Inst{7-0} = op2;
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}
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//===----------------------------------------------------------------------===//
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// S format
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//===----------------------------------------------------------------------===//
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class F_S<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<32> Inst;
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let Inst{31-16} = opcode;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12;
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}
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//===----------------------------------------------------------------------===//
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// SS format (1)
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//===----------------------------------------------------------------------===//
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class F_SS_1<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-32} = ll;
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//let Inst{31-28} = b1;
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//let Inst{27-16} = udisp12;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12_2;
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}
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//===----------------------------------------------------------------------===//
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// SS format (2)
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//===----------------------------------------------------------------------===//
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class F_SS_2<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = l1;
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//let Inst{35-32} = l2;
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//let Inst{31-28} = b1;
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//let Inst{27-16} = udisp12;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12_2;
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}
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//===----------------------------------------------------------------------===//
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// SS format (3)
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//===----------------------------------------------------------------------===//
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class F_SS_3<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = r3;
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//let Inst{31-28} = b1;
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//let Inst{27-16} = udisp12;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12_2;
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}
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//===----------------------------------------------------------------------===//
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// SS format (4)
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//===----------------------------------------------------------------------===//
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class F_SS_4<bits<8> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-40} = opcode;
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//let Inst{39-36} = r1;
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//let Inst{35-32} = r3;
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//let Inst{31-28} = b2;
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//let Inst{27-16} = udisp12_2;
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//let Inst{15-12} = b4;
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//let Inst{11-0} = udisp12_4;
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}
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//===----------------------------------------------------------------------===//
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// SSE format
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//===----------------------------------------------------------------------===//
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class F_SSE<bits<16> opcode,
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dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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let Inst{47-32} = opcode;
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//let Inst{31-28} = b1;
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//let Inst{27-16} = udisp12;
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//let Inst{15-12} = b2;
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//let Inst{11-0} = udisp12_2;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<outs, ins, asmstr, pattern> {
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|
}
|