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https://github.com/c64scene-ar/llvm-6502.git
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83e64baaef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25841 91177308-0d34-0410-b5e6-96231b3b80d8
463 lines
13 KiB
Plaintext
463 lines
13 KiB
Plaintext
TODO:
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* gpr0 allocation
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* implement do-loop -> bdnz transform
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* implement powerpc-64 for darwin
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* use stfiwx in float->int
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* Fold add and sub with constant into non-extern, non-weak addresses so this:
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lis r2, ha16(l2__ZTV4Cell)
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la r2, lo16(l2__ZTV4Cell)(r2)
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addi r2, r2, 8
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becomes:
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lis r2, ha16(l2__ZTV4Cell+8)
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la r2, lo16(l2__ZTV4Cell+8)(r2)
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* Teach LLVM how to codegen this:
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unsigned short foo(float a) { return a; }
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as:
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_foo:
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fctiwz f0,f1
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stfd f0,-8(r1)
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lhz r3,-2(r1)
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blr
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not:
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_foo:
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fctiwz f0, f1
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stfd f0, -8(r1)
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lwz r2, -4(r1)
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rlwinm r3, r2, 0, 16, 31
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blr
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* Support 'update' load/store instructions. These are cracked on the G5, but
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are still a codesize win.
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* should hint to the branch select pass that it doesn't need to print the
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second unconditional branch, so we don't end up with things like:
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b .LBBl42__2E_expand_function_8_674 ; loopentry.24
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b .LBBl42__2E_expand_function_8_42 ; NewDefault
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b .LBBl42__2E_expand_function_8_42 ; NewDefault
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===-------------------------------------------------------------------------===
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* Codegen this:
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void test2(int X) {
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if (X == 0x12345678) bar();
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}
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as:
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xoris r0,r3,0x1234
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cmpwi cr0,r0,0x5678
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beq cr0,L6
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not:
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lis r2, 4660
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ori r2, r2, 22136
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cmpw cr0, r3, r2
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bne .LBB_test2_2
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===-------------------------------------------------------------------------===
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Lump the constant pool for each function into ONE pic object, and reference
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pieces of it as offsets from the start. For functions like this (contrived
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to have lots of constants obviously):
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double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }
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We generate:
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_X:
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lis r2, ha16(.CPI_X_0)
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lfd f0, lo16(.CPI_X_0)(r2)
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lis r2, ha16(.CPI_X_1)
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lfd f2, lo16(.CPI_X_1)(r2)
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fmadd f0, f1, f0, f2
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lis r2, ha16(.CPI_X_2)
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lfd f1, lo16(.CPI_X_2)(r2)
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lis r2, ha16(.CPI_X_3)
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lfd f2, lo16(.CPI_X_3)(r2)
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fmadd f1, f0, f1, f2
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blr
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It would be better to materialize .CPI_X into a register, then use immediates
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off of the register to avoid the lis's. This is even more important in PIC
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mode.
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===-------------------------------------------------------------------------===
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Implement Newton-Rhapson method for improving estimate instructions to the
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correct accuracy, and implementing divide as multiply by reciprocal when it has
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more than one use. Itanium will want this too.
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===-------------------------------------------------------------------------===
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int foo(int a, int b) { return a == b ? 16 : 0; }
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_foo:
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cmpw cr7, r3, r4
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mfcr r2
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rlwinm r2, r2, 31, 31, 31
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slwi r3, r2, 4
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blr
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If we exposed the srl & mask ops after the MFCR that we are doing to select
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the correct CR bit, then we could fold the slwi into the rlwinm before it.
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===-------------------------------------------------------------------------===
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#define ARRAY_LENGTH 16
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union bitfield {
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struct {
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#ifndef __ppc__
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unsigned int field0 : 6;
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unsigned int field1 : 6;
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unsigned int field2 : 6;
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unsigned int field3 : 6;
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unsigned int field4 : 3;
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unsigned int field5 : 4;
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unsigned int field6 : 1;
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#else
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unsigned int field6 : 1;
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unsigned int field5 : 4;
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unsigned int field4 : 3;
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unsigned int field3 : 6;
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unsigned int field2 : 6;
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unsigned int field1 : 6;
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unsigned int field0 : 6;
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#endif
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} bitfields, bits;
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unsigned int u32All;
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signed int i32All;
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float f32All;
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};
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typedef struct program_t {
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union bitfield array[ARRAY_LENGTH];
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int size;
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int loaded;
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} program;
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void AdjustBitfields(program* prog, unsigned int fmt1)
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{
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unsigned int shift = 0;
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unsigned int texCount = 0;
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unsigned int i;
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for (i = 0; i < 8; i++)
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{
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prog->array[i].bitfields.field0 = texCount;
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prog->array[i].bitfields.field1 = texCount + 1;
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prog->array[i].bitfields.field2 = texCount + 2;
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prog->array[i].bitfields.field3 = texCount + 3;
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texCount += (fmt1 >> shift) & 0x7;
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shift += 3;
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}
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}
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In the loop above, the bitfield adds get generated as
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(add (shl bitfield, C1), (shl C2, C1)) where C2 is 1, 2 or 3.
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Since the input to the (or and, and) is an (add) rather than a (shl), the shift
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doesn't get folded into the rlwimi instruction. We should ideally see through
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things like this, rather than forcing llvm to generate the equivalent
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(shl (add bitfield, C2), C1) with some kind of mask.
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===-------------------------------------------------------------------------===
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Compile this:
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int %f1(int %a, int %b) {
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%tmp.1 = and int %a, 15 ; <int> [#uses=1]
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%tmp.3 = and int %b, 240 ; <int> [#uses=1]
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%tmp.4 = or int %tmp.3, %tmp.1 ; <int> [#uses=1]
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ret int %tmp.4
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}
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without a copy. We make this currently:
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_f1:
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rlwinm r2, r4, 0, 24, 27
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rlwimi r2, r3, 0, 28, 31
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or r3, r2, r2
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blr
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The two-addr pass or RA needs to learn when it is profitable to commute an
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instruction to avoid a copy AFTER the 2-addr instruction. The 2-addr pass
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currently only commutes to avoid inserting a copy BEFORE the two addr instr.
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===-------------------------------------------------------------------------===
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176.gcc contains a bunch of code like this (this occurs dozens of times):
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int %test(uint %mode.0.i.0) {
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%tmp.79 = cast uint %mode.0.i.0 to sbyte ; <sbyte> [#uses=1]
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%tmp.80 = cast sbyte %tmp.79 to int ; <int> [#uses=1]
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%tmp.81 = shl int %tmp.80, ubyte 16 ; <int> [#uses=1]
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%tmp.82 = and int %tmp.81, 16711680
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ret int %tmp.82
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}
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which we compile to:
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_test:
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extsb r2, r3
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rlwinm r3, r2, 16, 8, 15
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blr
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The extsb is obviously dead. This can be handled by a future thing like
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MaskedValueIsZero that checks to see if bits are ever demanded (in this case,
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the sign bits are never used, so we can fold the sext_inreg to nothing).
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I'm seeing code like this:
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srwi r3, r3, 16
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extsb r3, r3
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rlwimi r4, r3, 16, 8, 15
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in which the extsb is preventing the srwi from being nuked.
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===-------------------------------------------------------------------------===
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Another example that occurs is:
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uint %test(int %specbits.6.1) {
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%tmp.2540 = shr int %specbits.6.1, ubyte 11 ; <int> [#uses=1]
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%tmp.2541 = cast int %tmp.2540 to uint ; <uint> [#uses=1]
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%tmp.2542 = shl uint %tmp.2541, ubyte 13 ; <uint> [#uses=1]
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%tmp.2543 = and uint %tmp.2542, 8192 ; <uint> [#uses=1]
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ret uint %tmp.2543
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}
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which we codegen as:
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l1_test:
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srawi r2, r3, 11
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rlwinm r3, r2, 13, 18, 18
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blr
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the srawi can be nuked by turning the SAR into a logical SHR (the sext bits are
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dead), which I think can then be folded into the rlwinm.
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===-------------------------------------------------------------------------===
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Compile offsets from allocas:
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int *%test() {
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%X = alloca { int, int }
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%Y = getelementptr {int,int}* %X, int 0, uint 1
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ret int* %Y
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}
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into a single add, not two:
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_test:
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addi r2, r1, -8
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addi r3, r2, 4
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blr
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--> important for C++.
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===-------------------------------------------------------------------------===
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int test3(int a, int b) { return (a < 0) ? a : 0; }
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should be branch free code. LLVM is turning it into < 1 because of the RHS.
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===-------------------------------------------------------------------------===
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No loads or stores of the constants should be needed:
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struct foo { double X, Y; };
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void xxx(struct foo F);
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void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }
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===-------------------------------------------------------------------------===
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For this:
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int h(int i, int j, int k) {
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return (i==0||j==0||k == 0);
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}
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We currently emit this:
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_h:
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cntlzw r2, r3
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cntlzw r3, r4
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cntlzw r4, r5
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srwi r2, r2, 5
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srwi r3, r3, 5
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srwi r4, r4, 5
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or r2, r3, r2
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or r3, r2, r4
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blr
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The ctlz/shift instructions are created by the isel, so the dag combiner doesn't
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have a chance to pull the shifts through the or's (eliminating two
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instructions). SETCC nodes should be custom lowered in this case, not expanded
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by the isel.
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===-------------------------------------------------------------------------===
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Darwin Stub LICM optimization:
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Loops like this:
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for (...) bar();
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Have to go through an indirect stub if bar is external or linkonce. It would
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be better to compile it as:
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fp = &bar;
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for (...) fp();
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which only computes the address of bar once (instead of each time through the
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stub). This is Darwin specific and would have to be done in the code generator.
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Probably not a win on x86.
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===-------------------------------------------------------------------------===
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PowerPC i1/setcc stuff (depends on subreg stuff):
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Check out the PPC code we get for 'compare' in this testcase:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19672
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oof. on top of not doing the logical crnand instead of (mfcr, mfcr,
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invert, invert, or), we then have to compare it against zero instead of
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using the value already in a CR!
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that should be something like
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cmpw cr7, r8, r5
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cmpw cr0, r7, r3
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crnand cr0, cr0, cr7
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bne cr0, LBB_compare_4
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instead of
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cmpw cr7, r8, r5
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cmpw cr0, r7, r3
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mfcr r7, 1
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mcrf cr7, cr0
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mfcr r8, 1
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rlwinm r7, r7, 30, 31, 31
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rlwinm r8, r8, 30, 31, 31
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xori r7, r7, 1
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xori r8, r8, 1
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addi r2, r2, 1
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or r7, r8, r7
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cmpwi cr0, r7, 0
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bne cr0, LBB_compare_4 ; loopexit
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===-------------------------------------------------------------------------===
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Simple IPO for argument passing, change:
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void foo(int X, double Y, int Z) -> void foo(int X, int Z, double Y)
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the Darwin ABI specifies that any integer arguments in the first 32 bytes worth
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of arguments get assigned to r3 through r10. That is, if you have a function
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foo(int, double, int) you get r3, f1, r6, since the 64 bit double ate up the
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argument bytes for r4 and r5. The trick then would be to shuffle the argument
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order for functions we can internalize so that the maximum number of
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integers/pointers get passed in regs before you see any of the fp arguments.
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Instead of implementing this, it would actually probably be easier to just
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implement a PPC fastcc, where we could do whatever we wanted to the CC,
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including having this work sanely.
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===-------------------------------------------------------------------------===
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Fix Darwin FP-In-Integer Registers ABI
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Darwin passes doubles in structures in integer registers, which is very very
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bad. Add something like a BIT_CONVERT to LLVM, then do an i-p transformation
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that percolates these things out of functions.
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Check out how horrible this is:
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http://gcc.gnu.org/ml/gcc/2005-10/msg01036.html
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This is an extension of "interprocedural CC unmunging" that can't be done with
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just fastcc.
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===-------------------------------------------------------------------------===
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Code Gen IPO optimization:
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Squish small scalar globals together into a single global struct, allowing the
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address of the struct to be CSE'd, avoiding PIC accesses (also reduces the size
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of the GOT on targets with one).
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===-------------------------------------------------------------------------===
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Generate lwbrx and other byteswapping load/store instructions when reasonable.
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===-------------------------------------------------------------------------===
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Implement TargetConstantVec, and set up PPC to custom lower ConstantVec into
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TargetConstantVec's if it's one of the many forms that are algorithmically
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computable using the spiffy altivec instructions.
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===-------------------------------------------------------------------------===
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Compile this:
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double %test(double %X) {
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%Y = cast double %X to long
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%Z = cast long %Y to double
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ret double %Z
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}
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to this:
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_test:
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fctidz f0, f1
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stfd f0, -8(r1)
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lwz r2, -4(r1)
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lwz r3, -8(r1)
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stw r2, -12(r1)
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stw r3, -16(r1)
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lfd f0, -16(r1)
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fcfid f1, f0
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blr
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without the lwz/stw's.
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===-------------------------------------------------------------------------===
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Compile this:
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int foo(int a) {
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int b = (a < 8);
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if (b) {
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return b * 3; // ignore the fact that this is always 3.
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} else {
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return 2;
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}
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}
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into something not this:
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_foo:
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1) cmpwi cr7, r3, 8
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mfcr r2, 1
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rlwinm r2, r2, 29, 31, 31
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1) cmpwi cr0, r3, 7
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bgt cr0, LBB1_2 ; UnifiedReturnBlock
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LBB1_1: ; then
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rlwinm r2, r2, 0, 31, 31
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mulli r3, r2, 3
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blr
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LBB1_2: ; UnifiedReturnBlock
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li r3, 2
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blr
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In particular, the two compares (marked 1) could be shared by reversing one.
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This could be done in the dag combiner, by swapping a BR_CC when a SETCC of the
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same operands (but backwards) exists. In this case, this wouldn't save us
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anything though, because the compares still wouldn't be shared.
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