Kit Barton 1f9ea3a230 Change the generation of the vmuluwm instruction to be based on the MUL opcode. ... Phabricator review: http://reviews.llvm.org/D8185 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231827 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-10 19:49:38 +00:00
..
AArch64	[AArch64][LoadStoreOptimizer] Generate LDP + SXTW instead of LD[U]R + LD[U]RSW.	2015-03-06 22:42:10 +00:00
ARM	Remove use of misched-bench from this test and replace it with	2015-03-07 01:39:06 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Removing unused patterns.	2015-03-09 23:08:46 +00:00
Inputs
Mips	Reland r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation	2015-03-09 22:45:16 +00:00
MSP430
NVPTX
PowerPC	Change the generation of the vmuluwm instruction to be based on the MUL opcode.	2015-03-10 19:49:38 +00:00
R600	R600/SI: Limit SGPRs to 80 on Tonga and Iceland	2015-03-09 15:48:09 +00:00
SPARC
SystemZ
Thumb
Thumb2
WinEH	Replace llvm.frameallocate with llvm.frameescape	2015-03-05 18:26:34 +00:00
X86	Teach lowering to correctly handle invoke statepoint and gc results tied to them. Note that we still can not lower gc.relocates for invoke statepoints.	2015-03-10 16:26:48 +00:00
XCore	Reland r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation	2015-03-09 22:45:16 +00:00