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https://github.com/c64scene-ar/llvm-6502.git
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0115e164ba
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the opcode of the original operation without the load, not the load itself, MachineLICM needs to know the operand index in order to get the correct register class. Extend getOpcodeAfterMemoryUnfold to return this information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85622 91177308-0d34-0410-b5e6-96231b3b80d8
495 lines
18 KiB
C++
495 lines
18 KiB
C++
//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs loop invariant code motion on machine instructions. We
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// attempt to remove as much code from the body of a loop as possible.
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//
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// This pass does not attempt to throttle itself to limit register pressure.
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// The register allocation phases are expected to perform rematerialization
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// to recover when register pressure is high.
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//
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// This pass is not intended to be a replacement or a complete alternative
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// for the LLVM-IR-level LICM pass. It is only designed to hoist simple
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// constructs that are not exposed before lowering and instruction selection.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-licm"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
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STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
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namespace {
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class MachineLICM : public MachineFunctionPass {
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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BitVector AllocatableSet;
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// Various analyses that we use...
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AliasAnalysis *AA; // Alias analysis info.
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MachineLoopInfo *LI; // Current MachineLoopInfo
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MachineDominatorTree *DT; // Machine dominator tree for the cur loop
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MachineRegisterInfo *RegInfo; // Machine register information
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// State that is updated as we process loops
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bool Changed; // True if a loop is changed.
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MachineLoop *CurLoop; // The current loop we are working on.
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MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
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// For each BB and opcode pair, keep a list of hoisted instructions.
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DenseMap<std::pair<unsigned, unsigned>,
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std::vector<const MachineInstr*> > CSEMap;
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public:
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static char ID; // Pass identification, replacement for typeid
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MachineLICM() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const { return "Machine Instruction LICM"; }
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// FIXME: Loop preheaders?
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreserved<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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CSEMap.clear();
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}
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private:
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/// IsLoopInvariantInst - Returns true if the instruction is loop
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/// invariant. I.e., all virtual register operands are defined outside of
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/// the loop, physical registers aren't accessed (explicitly or implicitly),
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/// and the instruction is hoistable.
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///
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bool IsLoopInvariantInst(MachineInstr &I);
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/// IsProfitableToHoist - Return true if it is potentially profitable to
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/// hoist the given loop invariant.
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bool IsProfitableToHoist(MachineInstr &MI);
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/// HoistRegion - Walk the specified region of the CFG (defined by all
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/// blocks dominated by the specified block, and that are in the current
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/// loop) in depth first order w.r.t the DominatorTree. This allows us to
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/// visit definitions before uses, allowing us to hoist a loop body in one
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/// pass without iteration.
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///
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void HoistRegion(MachineDomTreeNode *N);
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/// ExtractHoistableLoad - Unfold a load from the given machineinstr if
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/// the load itself could be hoisted. Return the unfolded and hoistable
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/// load, or null if the load couldn't be unfolded or if it wouldn't
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/// be hoistable.
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MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
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/// Hoist - When an instruction is found to only use loop invariant operands
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/// that is safe to hoist, this instruction is called to do the dirty work.
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///
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void Hoist(MachineInstr *MI);
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};
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} // end anonymous namespace
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char MachineLICM::ID = 0;
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static RegisterPass<MachineLICM>
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X("machinelicm", "Machine Loop Invariant Code Motion");
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FunctionPass *llvm::createMachineLICMPass() { return new MachineLICM(); }
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/// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most
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/// loop that has a preheader.
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static bool LoopIsOuterMostWithPreheader(MachineLoop *CurLoop) {
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for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
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if (L->getLoopPreheader())
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return false;
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return true;
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}
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/// Hoist expressions out of the specified loop. Note, alias info for inner loop
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/// is not preserved so it is not a good idea to run LICM multiple times on one
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/// loop.
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///
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bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(errs() << "******** Machine LICM ********\n");
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Changed = false;
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TM = &MF.getTarget();
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TII = TM->getInstrInfo();
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TRI = TM->getRegisterInfo();
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RegInfo = &MF.getRegInfo();
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AllocatableSet = TRI->getAllocatableSet(MF);
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// Get our Loop information...
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LI = &getAnalysis<MachineLoopInfo>();
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DT = &getAnalysis<MachineDominatorTree>();
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AA = &getAnalysis<AliasAnalysis>();
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for (MachineLoopInfo::iterator
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I = LI->begin(), E = LI->end(); I != E; ++I) {
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CurLoop = *I;
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// Only visit outer-most preheader-sporting loops.
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if (!LoopIsOuterMostWithPreheader(CurLoop))
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continue;
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// Determine the block to which to hoist instructions. If we can't find a
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// suitable loop preheader, we can't do any hoisting.
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//
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// FIXME: We are only hoisting if the basic block coming into this loop
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// has only one successor. This isn't the case in general because we haven't
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// broken critical edges or added preheaders.
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CurPreheader = CurLoop->getLoopPreheader();
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if (!CurPreheader)
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continue;
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HoistRegion(DT->getNode(CurLoop->getHeader()));
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}
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return Changed;
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}
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/// HoistRegion - Walk the specified region of the CFG (defined by all blocks
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/// dominated by the specified block, and that are in the current loop) in depth
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/// first order w.r.t the DominatorTree. This allows us to visit definitions
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/// before uses, allowing us to hoist a loop body in one pass without iteration.
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///
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void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
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assert(N != 0 && "Null dominator tree node?");
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MachineBasicBlock *BB = N->getBlock();
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// If this subregion is not in the top level loop at all, exit.
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if (!CurLoop->contains(BB)) return;
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for (MachineBasicBlock::iterator
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MII = BB->begin(), E = BB->end(); MII != E; ) {
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MachineBasicBlock::iterator NextMII = MII; ++NextMII;
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MachineInstr &MI = *MII;
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Hoist(&MI);
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MII = NextMII;
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}
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const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
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for (unsigned I = 0, E = Children.size(); I != E; ++I)
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HoistRegion(Children[I]);
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}
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/// IsLoopInvariantInst - Returns true if the instruction is loop
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/// invariant. I.e., all virtual register operands are defined outside of the
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/// loop, physical registers aren't accessed explicitly, and there are no side
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/// effects that aren't captured by the operands or other flags.
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///
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bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
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const TargetInstrDesc &TID = I.getDesc();
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// Ignore stuff that we obviously can't hoist.
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if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
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TID.hasUnmodeledSideEffects())
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return false;
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if (TID.mayLoad()) {
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// Okay, this instruction does a load. As a refinement, we allow the target
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// to decide whether the loaded value is actually a constant. If so, we can
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// actually use it as a load.
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if (!I.isInvariantLoad(AA))
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// FIXME: we should be able to sink loads with no other side effects if
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// there is nothing that can change memory from here until the end of
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// block. This is a trivial form of alias analysis.
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return false;
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}
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DEBUG({
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errs() << "--- Checking if we can hoist " << I;
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if (I.getDesc().getImplicitUses()) {
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errs() << " * Instruction has implicit uses:\n";
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const TargetRegisterInfo *TRI = TM->getRegisterInfo();
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for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
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*ImpUses; ++ImpUses)
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errs() << " -> " << TRI->getName(*ImpUses) << "\n";
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}
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if (I.getDesc().getImplicitDefs()) {
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errs() << " * Instruction has implicit defines:\n";
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const TargetRegisterInfo *TRI = TM->getRegisterInfo();
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for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
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*ImpDefs; ++ImpDefs)
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errs() << " -> " << TRI->getName(*ImpDefs) << "\n";
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}
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});
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if (I.getDesc().getImplicitDefs() || I.getDesc().getImplicitUses()) {
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DEBUG(errs() << "Cannot hoist with implicit defines or uses\n");
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return false;
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}
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// The instruction is loop invariant if all of its operands are.
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for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = I.getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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// Don't hoist an instruction that uses or defines a physical register.
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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if (MO.isUse()) {
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// If the physreg has no defs anywhere, it's just an ambient register
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// and we can freely move its uses. Alternatively, if it's allocatable,
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// it could get allocated to something with a def during allocation.
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if (!RegInfo->def_empty(Reg))
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return false;
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if (AllocatableSet.test(Reg))
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return false;
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// Check for a def among the register's aliases too.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (!RegInfo->def_empty(AliasReg))
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return false;
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if (AllocatableSet.test(AliasReg))
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return false;
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}
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// Otherwise it's safe to move.
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continue;
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} else if (!MO.isDead()) {
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// A def that isn't dead. We can't move it.
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return false;
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}
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}
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if (!MO.isUse())
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continue;
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assert(RegInfo->getVRegDef(Reg) &&
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"Machine instr not mapped for this vreg?!");
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// If the loop contains the definition of an operand, then the instruction
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// isn't loop invariant.
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if (CurLoop->contains(RegInfo->getVRegDef(Reg)->getParent()))
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return false;
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}
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// If we got this far, the instruction is loop invariant!
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return true;
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}
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/// HasPHIUses - Return true if the specified register has any PHI use.
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static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
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for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg),
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UE = RegInfo->use_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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if (UseMI->getOpcode() == TargetInstrInfo::PHI)
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return true;
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}
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return false;
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}
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/// IsProfitableToHoist - Return true if it is potentially profitable to hoist
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/// the given loop invariant.
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bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
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if (MI.getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
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return false;
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// FIXME: For now, only hoist re-materilizable instructions. LICM will
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// increase register pressure. We want to make sure it doesn't increase
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// spilling.
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if (!TII->isTriviallyReMaterializable(&MI, AA))
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return false;
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// If result(s) of this instruction is used by PHIs, then don't hoist it.
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// The presence of joins makes it difficult for current register allocator
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// implementation to perform remat.
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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if (HasPHIUses(MO.getReg(), RegInfo))
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return false;
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}
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return true;
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}
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static const MachineInstr *LookForDuplicate(const MachineInstr *MI,
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std::vector<const MachineInstr*> &PrevMIs,
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MachineRegisterInfo *RegInfo) {
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unsigned NumOps = MI->getNumOperands();
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for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
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const MachineInstr *PrevMI = PrevMIs[i];
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unsigned NumOps2 = PrevMI->getNumOperands();
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if (NumOps != NumOps2)
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continue;
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bool IsSame = true;
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for (unsigned j = 0; j != NumOps; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (MO.isReg() && MO.isDef()) {
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if (RegInfo->getRegClass(MO.getReg()) !=
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RegInfo->getRegClass(PrevMI->getOperand(j).getReg())) {
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IsSame = false;
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break;
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}
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continue;
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}
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if (!MO.isIdenticalTo(PrevMI->getOperand(j))) {
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IsSame = false;
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break;
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}
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}
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if (IsSame)
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return PrevMI;
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}
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return 0;
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}
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MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
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// If not, we may be able to unfold a load and hoist that.
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// First test whether the instruction is loading from an amenable
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// memory location.
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if (!MI->getDesc().mayLoad()) return 0;
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if (!MI->hasOneMemOperand()) return 0;
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MachineMemOperand *MMO = *MI->memoperands_begin();
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if (MMO->isVolatile()) return 0;
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MachineFunction &MF = *MI->getParent()->getParent();
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if (!MMO->getValue()) return 0;
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if (const PseudoSourceValue *PSV =
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dyn_cast<PseudoSourceValue>(MMO->getValue())) {
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if (!PSV->isConstant(MF.getFrameInfo())) return 0;
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} else {
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if (!AA->pointsToConstantMemory(MMO->getValue())) return 0;
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}
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// Next determine the register class for a temporary register.
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unsigned LoadRegIndex;
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unsigned NewOpc =
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TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
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/*UnfoldLoad=*/true,
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/*UnfoldStore=*/false,
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&LoadRegIndex);
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if (NewOpc == 0) return 0;
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const TargetInstrDesc &TID = TII->get(NewOpc);
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if (TID.getNumDefs() != 1) return 0;
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const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
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// Ok, we're unfolding. Create a temporary register and do the unfold.
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unsigned Reg = RegInfo->createVirtualRegister(RC);
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SmallVector<MachineInstr *, 2> NewMIs;
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bool Success =
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TII->unfoldMemoryOperand(MF, MI, Reg,
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/*UnfoldLoad=*/true, /*UnfoldStore=*/false,
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NewMIs);
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(void)Success;
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assert(Success &&
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"unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
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"succeeded!");
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assert(NewMIs.size() == 2 &&
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"Unfolded a load into multiple instructions!");
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MachineBasicBlock *MBB = MI->getParent();
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MBB->insert(MI, NewMIs[0]);
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MBB->insert(MI, NewMIs[1]);
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// If unfolding produced a load that wasn't loop-invariant or profitable to
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// hoist, discard the new instructions and bail.
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if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
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NewMIs[0]->eraseFromParent();
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NewMIs[1]->eraseFromParent();
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return 0;
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}
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// Otherwise we successfully unfolded a load that we can hoist.
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MI->eraseFromParent();
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return NewMIs[0];
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}
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/// Hoist - When an instruction is found to use only loop invariant operands
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/// that are safe to hoist, this instruction is called to do the dirty work.
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///
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void MachineLICM::Hoist(MachineInstr *MI) {
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// First check whether we should hoist this instruction.
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if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
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// If not, try unfolding a hoistable load.
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MI = ExtractHoistableLoad(MI);
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if (!MI) return;
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}
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// Now move the instructions to the predecessor, inserting it before any
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// terminator instructions.
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DEBUG({
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errs() << "Hoisting " << *MI;
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if (CurPreheader->getBasicBlock())
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errs() << " to MachineBasicBlock "
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<< CurPreheader->getBasicBlock()->getName();
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if (MI->getParent()->getBasicBlock())
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errs() << " from MachineBasicBlock "
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<< MI->getParent()->getBasicBlock()->getName();
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errs() << "\n";
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});
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// Look for opportunity to CSE the hoisted instruction.
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std::pair<unsigned, unsigned> BBOpcPair =
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std::make_pair(CurPreheader->getNumber(), MI->getOpcode());
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DenseMap<std::pair<unsigned, unsigned>,
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std::vector<const MachineInstr*> >::iterator CI = CSEMap.find(BBOpcPair);
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bool DoneCSE = false;
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if (CI != CSEMap.end()) {
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const MachineInstr *Dup = LookForDuplicate(MI, CI->second, RegInfo);
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if (Dup) {
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DEBUG(errs() << "CSEing " << *MI << " with " << *Dup);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef())
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RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
|
|
}
|
|
MI->eraseFromParent();
|
|
DoneCSE = true;
|
|
++NumCSEed;
|
|
}
|
|
}
|
|
|
|
// Otherwise, splice the instruction to the preheader.
|
|
if (!DoneCSE) {
|
|
CurPreheader->splice(CurPreheader->getFirstTerminator(),
|
|
MI->getParent(), MI);
|
|
// Add to the CSE map.
|
|
if (CI != CSEMap.end())
|
|
CI->second.push_back(MI);
|
|
else {
|
|
std::vector<const MachineInstr*> CSEMIs;
|
|
CSEMIs.push_back(MI);
|
|
CSEMap.insert(std::make_pair(BBOpcPair, CSEMIs));
|
|
}
|
|
}
|
|
|
|
++NumHoisted;
|
|
Changed = true;
|
|
}
|