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A RegisterTuples instance is used to synthesize super-registers by zipping together lists of sub-registers. This is useful for generating pseudo-registers representing register sequence constraints like 'two consecutive GPRs', or 'an even-odd pair of floating point registers'. The RegisterTuples def can be used in register set operations when building register classes. That is the only way of accessing the synthesized super-registers. For example, the ARM QQ register class of pseudo-registers could have been formed like this: // Form pairs Q0_Q1, Q2_Q3, ... def QQPairs : RegisterTuples<[qsub_0, qsub_1], [(decimate QPR, 2), (decimate (shl QPR, 1), 2)]>; def QQ : RegisterClass<..., (add QQPairs)>; Similarly, pseudo-registers representing '3 consecutive D-regs with wraparound' look like: // Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1. def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2], [(rotl DPR, 0), (rotl DPR, 1), (rotl DPR, 2)]>; TableGen automatically computes aliasing information for the synthesized registers. Register tuples are still somewhat experimental. We still need to see how they interact with MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133407 91177308-0d34-0410-b5e6-96231b3b80d8 |
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