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4d13f315d1
llvm-6502/lib/Target/R600
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Daniel Sanders 4d13f315d1 Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC. 
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10311


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239467 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 12:11:26 +00:00
..
AsmParser MC: Clean up MCExpr naming. NFC. 2015-05-30 01:25:56 +00:00
InstPrinter MC: Add target hook to control symbol quoting 2015-06-09 00:31:39 +00:00
MCTargetDesc Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC. 2015-06-10 12:11:26 +00:00
TargetInfo
AMDGPU.h Fix clang-cl self-host -Wc++11-narrowing bug 2015-06-08 21:57:57 +00:00
AMDGPU.td R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips 2015-05-25 16:15:54 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFC 2015-06-08 20:09:58 +00:00
AMDGPUInstrInfo.h [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFC 2015-06-08 20:09:58 +00:00
AMDGPUInstrInfo.td R600: Switch to using generic min / max nodes. 2015-06-09 00:52:37 +00:00
AMDGPUInstructions.td
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp
AMDGPUISelLowering.cpp R600: Switch to using generic min / max nodes. 2015-06-09 00:52:37 +00:00
AMDGPUISelLowering.h R600: Switch to using generic min / max nodes. 2015-06-09 00:52:37 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp MC: Clean up MCExpr naming. NFC. 2015-05-30 01:25:56 +00:00
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC. 2015-06-10 12:11:26 +00:00
AMDGPUSubtarget.h Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC. 2015-06-10 12:11:26 +00:00
AMDGPUTargetMachine.cpp Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC. 2015-06-10 12:11:26 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDGPUTargetTransformInfo.h
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
CaymanInstructions.td
CIInstructions.td
CMakeLists.txt
EvergreenInstructions.td
LLVMBuild.txt
Makefile
Processors.td R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips 2015-05-25 16:15:54 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td R600: Switch to using generic min / max nodes. 2015-06-09 00:52:37 +00:00
R600Intrinsics.td
R600ISelLowering.cpp R600: Rely on TypeLegalizer to use divrem instead of div/rem 2015-05-27 16:54:10 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixControlFlowLiveIntervals.cpp
SIFixSGPRCopies.cpp
SIFixSGPRLiveRanges.cpp
SIFoldOperands.cpp
SIInsertWaits.cpp
SIInstrFormats.td
SIInstrInfo.cpp
SIInstrInfo.h
SIInstrInfo.td R600/SI: Add assembler support for all CI and VI VOP2 instructions 2015-05-26 15:55:52 +00:00
SIInstructions.td R600: Switch to using generic min / max nodes. 2015-06-09 00:52:37 +00:00
SIIntrinsics.td
SIISelLowering.cpp R600: Switch to using generic min / max nodes. 2015-06-09 00:52:37 +00:00
SIISelLowering.h Add address space argument to isLegalAddressingMode 2015-06-01 05:31:59 +00:00
SILoadStoreOptimizer.cpp
SILowerControlFlow.cpp
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIPrepareScratchRegs.cpp
SIRegisterInfo.cpp
SIRegisterInfo.h
SIRegisterInfo.td
SISchedule.td
SIShrinkInstructions.cpp
SITypeRewriter.cpp
VIInstrFormats.td
VIInstructions.td R600/SI: Add assembler support for all CI and VI VOP2 instructions 2015-05-26 15:55:52 +00:00