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156 lines
5.8 KiB
C++
156 lines
5.8 KiB
C++
//===- X86Disassembler.h - Disassembler for x86 and x86_64 ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
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// 64-bit X86 instruction sets. The main decode sequence for an assembly
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// instruction in this disassembler is:
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//
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// 1. Read the prefix bytes and determine the attributes of the instruction.
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// These attributes, recorded in enum attributeBits
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// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM
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// provides a mapping from bitmasks to contexts, which are represented by
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// enum InstructionContext (ibid.).
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//
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// 2. Read the opcode, and determine what kind of opcode it is. The
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// disassembler distinguishes four kinds of opcodes, which are enumerated in
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// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte
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// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a
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// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context.
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//
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// 3. Depending on the opcode type, look in one of four ClassDecision structures
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// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which
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// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get
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// a ModRMDecision (ibid.).
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//
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// 4. Some instructions, such as escape opcodes or extended opcodes, or even
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// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the
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// ModR/M byte to complete decode. The ModRMDecision's type is an entry from
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// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the
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// ModR/M byte is required and how to interpret it.
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//
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// 5. After resolving the ModRMDecision, the disassembler has a unique ID
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// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in
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// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
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// meanings of its operands.
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//
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// 6. For each operand, its encoding is an entry from OperandEncoding
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// (X86DisassemblerDecoderCommon.h) and its type is an entry from
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// OperandType (ibid.). The encoding indicates how to read it from the
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// instruction; the type indicates how to interpret the value once it has
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// been read. For example, a register operand could be stored in the R/M
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// field of the ModR/M byte, the REG field of the ModR/M byte, or added to
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// the main opcode. This is orthogonal from its meaning (an GPR or an XMM
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// register, for instance). Given this information, the operands can be
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// extracted and interpreted.
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//
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// 7. As the last step, the disassembler translates the instruction information
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// and operands into a format understandable by the client - in this case, an
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// MCInst for use by the MC infrastructure.
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//
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// The disassembler is broken broadly into two parts: the table emitter that
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// emits the instruction decode tables discussed above during compilation, and
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// the disassembler itself. The table emitter is documented in more detail in
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// utils/TableGen/X86DisassemblerEmitter.h.
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//
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// X86Disassembler.h contains the public interface for the disassembler,
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// adhering to the MCDisassembler interface.
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// X86Disassembler.cpp contains the code responsible for step 7, and for
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// invoking the decoder to execute steps 1-6.
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// X86DisassemblerDecoderCommon.h contains the definitions needed by both the
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// table emitter and the disassembler.
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// X86DisassemblerDecoder.h contains the public interface of the decoder,
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// factored out into C for possible use by other projects.
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// X86DisassemblerDecoder.c contains the source code of the decoder, which is
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// responsible for steps 1-6.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86DISASSEMBLER_H
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#define X86DISASSEMBLER_H
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#define INSTRUCTION_SPECIFIER_FIELDS \
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const char* name;
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#define INSTRUCTION_IDS \
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const InstrUID *instructionIDs;
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#include "X86DisassemblerDecoderCommon.h"
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#undef INSTRUCTION_SPECIFIER_FIELDS
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#undef INSTRUCTION_IDS
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#include "llvm/MC/MCDisassembler.h"
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struct InternalInstruction;
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namespace llvm {
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class MCInst;
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class MemoryObject;
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class raw_ostream;
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struct EDInstInfo;
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namespace X86Disassembler {
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/// X86GenericDisassembler - Generic disassembler for all X86 platforms.
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/// All each platform class should have to do is subclass the constructor, and
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/// provide a different disassemblerMode value.
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class X86GenericDisassembler : public MCDisassembler {
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protected:
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/// Constructor - Initializes the disassembler.
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///
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/// @param mode - The X86 architecture mode to decode for.
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X86GenericDisassembler(DisassemblerMode mode);
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public:
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~X86GenericDisassembler();
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/// getInstruction - See MCDisassembler.
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bool getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream) const;
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/// getEDInfo - See MCDisassembler.
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EDInstInfo *getEDInfo() const;
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private:
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DisassemblerMode fMode;
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};
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/// X86_16Disassembler - 16-bit X86 disassembler.
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class X86_16Disassembler : public X86GenericDisassembler {
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public:
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X86_16Disassembler() :
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X86GenericDisassembler(MODE_16BIT) {
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}
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};
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/// X86_16Disassembler - 32-bit X86 disassembler.
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class X86_32Disassembler : public X86GenericDisassembler {
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public:
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X86_32Disassembler() :
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X86GenericDisassembler(MODE_32BIT) {
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}
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};
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/// X86_16Disassembler - 64-bit X86 disassembler.
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class X86_64Disassembler : public X86GenericDisassembler {
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public:
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X86_64Disassembler() :
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X86GenericDisassembler(MODE_64BIT) {
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}
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};
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} // namespace X86Disassembler
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} // namespace llvm
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#endif
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