Hao Liu 591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). ... Including following 14 instructions: 4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8		2013-11-05 03:39:32 +00:00
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AArch64	Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).	2013-11-05 03:39:32 +00:00
ARM	Test cleanup for v8 instructions	2013-10-29 14:16:09 +00:00
AsmParser
COFF
Disassembler	Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).	2013-11-05 03:39:32 +00:00
ELF	This commit adds some (but not all) of the x86-64 relocations that are not	2013-10-30 18:47:25 +00:00
MachO
Markup
Mips	Support for microMIPS branch instructions.	2013-11-04 14:53:22 +00:00
PowerPC	Convert another llc -filetype=obj test.	2013-10-28 22:17:19 +00:00
SystemZ
X86