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Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
739 lines
23 KiB
C++
739 lines
23 KiB
C++
//===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Simple pass to fill delay slots with useful instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/MipsMCNaCl.h"
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "delay-slot-filler"
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STATISTIC(FilledSlots, "Number of delay slots filled");
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STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
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" are not NOP.");
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static cl::opt<bool> DisableDelaySlotFiller(
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"disable-mips-delay-filler",
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cl::init(false),
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cl::desc("Fill all delay slots with NOPs."),
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cl::Hidden);
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static cl::opt<bool> DisableForwardSearch(
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"disable-mips-df-forward-search",
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cl::init(true),
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cl::desc("Disallow MIPS delay filler to search forward."),
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cl::Hidden);
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static cl::opt<bool> DisableSuccBBSearch(
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"disable-mips-df-succbb-search",
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cl::init(true),
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cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
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cl::Hidden);
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static cl::opt<bool> DisableBackwardSearch(
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"disable-mips-df-backward-search",
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cl::init(false),
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cl::desc("Disallow MIPS delay filler to search backward."),
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cl::Hidden);
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namespace {
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typedef MachineBasicBlock::iterator Iter;
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typedef MachineBasicBlock::reverse_iterator ReverseIter;
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typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap;
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class RegDefsUses {
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public:
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RegDefsUses(TargetMachine &TM);
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void init(const MachineInstr &MI);
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/// This function sets all caller-saved registers in Defs.
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void setCallerSaved(const MachineInstr &MI);
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/// This function sets all unallocatable registers in Defs.
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void setUnallocatableRegs(const MachineFunction &MF);
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/// Set bits in Uses corresponding to MBB's live-out registers except for
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/// the registers that are live-in to SuccBB.
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void addLiveOut(const MachineBasicBlock &MBB,
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const MachineBasicBlock &SuccBB);
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bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
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private:
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bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
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bool IsDef) const;
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/// Returns true if Reg or its alias is in RegSet.
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bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
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const TargetRegisterInfo &TRI;
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BitVector Defs, Uses;
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};
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/// Base class for inspecting loads and stores.
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class InspectMemInstr {
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public:
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InspectMemInstr(bool ForbidMemInstr_)
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: OrigSeenLoad(false), OrigSeenStore(false), SeenLoad(false),
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SeenStore(false), ForbidMemInstr(ForbidMemInstr_) {}
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/// Return true if MI cannot be moved to delay slot.
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bool hasHazard(const MachineInstr &MI);
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virtual ~InspectMemInstr() {}
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protected:
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/// Flags indicating whether loads or stores have been seen.
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bool OrigSeenLoad, OrigSeenStore, SeenLoad, SeenStore;
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/// Memory instructions are not allowed to move to delay slot if this flag
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/// is true.
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bool ForbidMemInstr;
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private:
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virtual bool hasHazard_(const MachineInstr &MI) = 0;
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};
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/// This subclass rejects any memory instructions.
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class NoMemInstr : public InspectMemInstr {
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public:
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NoMemInstr() : InspectMemInstr(true) {}
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private:
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bool hasHazard_(const MachineInstr &MI) override { return true; }
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};
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/// This subclass accepts loads from stacks and constant loads.
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class LoadFromStackOrConst : public InspectMemInstr {
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public:
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LoadFromStackOrConst() : InspectMemInstr(false) {}
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private:
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bool hasHazard_(const MachineInstr &MI) override;
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};
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/// This subclass uses memory dependence information to determine whether a
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/// memory instruction can be moved to a delay slot.
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class MemDefsUses : public InspectMemInstr {
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public:
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MemDefsUses(const MachineFrameInfo *MFI);
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private:
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typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
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bool hasHazard_(const MachineInstr &MI) override;
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/// Update Defs and Uses. Return true if there exist dependences that
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/// disqualify the delay slot candidate between V and values in Uses and
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/// Defs.
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bool updateDefsUses(ValueType V, bool MayStore);
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/// Get the list of underlying objects of MI's memory operand.
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bool getUnderlyingObjects(const MachineInstr &MI,
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SmallVectorImpl<ValueType> &Objects) const;
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const MachineFrameInfo *MFI;
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SmallPtrSet<ValueType, 4> Uses, Defs;
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/// Flags indicating whether loads or stores with no underlying objects have
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/// been seen.
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bool SeenNoObjLoad, SeenNoObjStore;
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};
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class Filler : public MachineFunctionPass {
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public:
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Filler(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm) { }
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const char *getPassName() const override {
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return "Mips Delay Slot Filler";
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}
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bool runOnMachineFunction(MachineFunction &F) override {
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bool Changed = false;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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// This pass invalidates liveness information when it reorders
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// instructions to fill delay slot. Without this, -verify-machineinstrs
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// will fail.
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if (Changed)
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F.getRegInfo().invalidateLiveness();
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return Changed;
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineBranchProbabilityInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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/// This function checks if it is valid to move Candidate to the delay slot
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/// and returns true if it isn't. It also updates memory and register
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/// dependence information.
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bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
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InspectMemInstr &IM) const;
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/// This function searches range [Begin, End) for an instruction that can be
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/// moved to the delay slot. Returns true on success.
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template<typename IterTy>
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bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
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RegDefsUses &RegDU, InspectMemInstr &IM,
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IterTy &Filler) const;
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/// This function searches in the backward direction for an instruction that
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/// can be moved to the delay slot. Returns true on success.
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bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const;
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/// This function searches MBB in the forward direction for an instruction
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/// that can be moved to the delay slot. Returns true on success.
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bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
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/// This function searches one of MBB's successor blocks for an instruction
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/// that can be moved to the delay slot and inserts clones of the
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/// instruction into the successor's predecessor blocks.
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bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
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/// Pick a successor block of MBB. Return NULL if MBB doesn't have a
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/// successor block that is not a landing pad.
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MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const;
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/// This function analyzes MBB and returns an instruction with an unoccupied
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/// slot that branches to Dst.
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std::pair<MipsInstrInfo::BranchType, MachineInstr *>
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getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const;
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/// Examine Pred and see if it is possible to insert an instruction into
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/// one of its branches delay slot or its end.
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bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
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RegDefsUses &RegDU, bool &HasMultipleSuccs,
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BB2BrMap &BrMap) const;
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bool terminateSearch(const MachineInstr &Candidate) const;
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TargetMachine &TM;
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static char ID;
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};
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char Filler::ID = 0;
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} // end of anonymous namespace
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static bool hasUnoccupiedSlot(const MachineInstr *MI) {
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return MI->hasDelaySlot() && !MI->isBundledWithSucc();
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}
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/// This function inserts clones of Filler into predecessor blocks.
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static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
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MachineFunction *MF = Filler->getParent()->getParent();
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for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
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if (I->second) {
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MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
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++UsefulSlots;
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} else {
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I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
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}
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}
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}
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/// This function adds registers Filler defines to MBB's live-in register list.
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static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
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for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = Filler->getOperand(I);
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unsigned R;
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if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
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continue;
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#ifndef NDEBUG
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const MachineFunction &MF = *MBB.getParent();
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assert(MF.getTarget().getRegisterInfo()->getAllocatableSet(MF).test(R) &&
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"Shouldn't move an instruction with unallocatable registers across "
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"basic block boundaries.");
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#endif
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if (!MBB.isLiveIn(R))
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MBB.addLiveIn(R);
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}
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}
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RegDefsUses::RegDefsUses(TargetMachine &TM)
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: TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false),
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Uses(TRI.getNumRegs(), false) {}
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void RegDefsUses::init(const MachineInstr &MI) {
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// Add all register operands which are explicit and non-variadic.
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update(MI, 0, MI.getDesc().getNumOperands());
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// If MI is a call, add RA to Defs to prevent users of RA from going into
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// delay slot.
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if (MI.isCall())
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Defs.set(Mips::RA);
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// Add all implicit register operands of branch instructions except
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// register AT.
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if (MI.isBranch()) {
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update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
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Defs.reset(Mips::AT);
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}
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}
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void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
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assert(MI.isCall());
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// If MI is a call, add all caller-saved registers to Defs.
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BitVector CallerSavedRegs(TRI.getNumRegs(), true);
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CallerSavedRegs.reset(Mips::ZERO);
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CallerSavedRegs.reset(Mips::ZERO_64);
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for (const MCPhysReg *R = TRI.getCalleeSavedRegs(); *R; ++R)
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for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
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CallerSavedRegs.reset(*AI);
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Defs |= CallerSavedRegs;
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}
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void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
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BitVector AllocSet = TRI.getAllocatableSet(MF);
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for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R))
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for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
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AllocSet.set(*AI);
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AllocSet.set(Mips::ZERO);
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AllocSet.set(Mips::ZERO_64);
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Defs |= AllocSet.flip();
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}
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void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
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const MachineBasicBlock &SuccBB) {
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for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
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SE = MBB.succ_end(); SI != SE; ++SI)
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if (*SI != &SuccBB)
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for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
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LE = (*SI)->livein_end(); LI != LE; ++LI)
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Uses.set(*LI);
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}
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bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
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BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
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bool HasHazard = false;
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for (unsigned I = Begin; I != End; ++I) {
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const MachineOperand &MO = MI.getOperand(I);
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if (MO.isReg() && MO.getReg())
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HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
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}
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Defs |= NewDefs;
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Uses |= NewUses;
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return HasHazard;
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}
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bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
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unsigned Reg, bool IsDef) const {
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if (IsDef) {
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NewDefs.set(Reg);
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// check whether Reg has already been defined or used.
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return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
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}
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NewUses.set(Reg);
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// check whether Reg has already been defined.
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return isRegInSet(Defs, Reg);
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}
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bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
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// Check Reg and all aliased Registers.
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for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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if (RegSet.test(*AI))
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return true;
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return false;
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}
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bool InspectMemInstr::hasHazard(const MachineInstr &MI) {
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if (!MI.mayStore() && !MI.mayLoad())
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return false;
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if (ForbidMemInstr)
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return true;
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OrigSeenLoad = SeenLoad;
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OrigSeenStore = SeenStore;
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SeenLoad |= MI.mayLoad();
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SeenStore |= MI.mayStore();
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// If MI is an ordered or volatile memory reference, disallow moving
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// subsequent loads and stores to delay slot.
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if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
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ForbidMemInstr = true;
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return true;
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}
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return hasHazard_(MI);
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}
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bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) {
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if (MI.mayStore())
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return true;
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if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getPseudoValue())
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return true;
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if (const PseudoSourceValue *PSV =
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(*MI.memoperands_begin())->getPseudoValue()) {
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if (isa<FixedStackPseudoSourceValue>(PSV))
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return false;
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return !PSV->isConstant(nullptr) && PSV != PseudoSourceValue::getStack();
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}
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return true;
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}
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MemDefsUses::MemDefsUses(const MachineFrameInfo *MFI_)
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: InspectMemInstr(false), MFI(MFI_), SeenNoObjLoad(false),
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SeenNoObjStore(false) {}
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bool MemDefsUses::hasHazard_(const MachineInstr &MI) {
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bool HasHazard = false;
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SmallVector<ValueType, 4> Objs;
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// Check underlying object list.
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if (getUnderlyingObjects(MI, Objs)) {
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for (SmallVectorImpl<ValueType>::const_iterator I = Objs.begin();
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I != Objs.end(); ++I)
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HasHazard |= updateDefsUses(*I, MI.mayStore());
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return HasHazard;
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}
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// No underlying objects found.
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HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
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HasHazard |= MI.mayLoad() || OrigSeenStore;
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SeenNoObjLoad |= MI.mayLoad();
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SeenNoObjStore |= MI.mayStore();
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return HasHazard;
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}
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bool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) {
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if (MayStore)
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return !Defs.insert(V) || Uses.count(V) || SeenNoObjStore || SeenNoObjLoad;
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Uses.insert(V);
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return Defs.count(V) || SeenNoObjStore;
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}
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bool MemDefsUses::
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getUnderlyingObjects(const MachineInstr &MI,
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SmallVectorImpl<ValueType> &Objects) const {
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if (!MI.hasOneMemOperand() ||
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(!(*MI.memoperands_begin())->getValue() &&
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!(*MI.memoperands_begin())->getPseudoValue()))
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return false;
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if (const PseudoSourceValue *PSV =
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(*MI.memoperands_begin())->getPseudoValue()) {
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if (!PSV->isAliased(MFI))
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return false;
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Objects.push_back(PSV);
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return true;
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}
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const Value *V = (*MI.memoperands_begin())->getValue();
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SmallVector<Value *, 4> Objs;
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GetUnderlyingObjects(const_cast<Value *>(V), Objs);
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for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), E = Objs.end();
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I != E; ++I) {
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if (!isIdentifiedObject(V))
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return false;
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|
Objects.push_back(*I);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
|
|
/// We assume there is only one delay slot per delayed instruction.
|
|
bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
|
|
bool Changed = false;
|
|
|
|
for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
|
|
if (!hasUnoccupiedSlot(&*I))
|
|
continue;
|
|
|
|
++FilledSlots;
|
|
Changed = true;
|
|
|
|
// Delay slot filling is disabled at -O0.
|
|
if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
|
|
if (searchBackward(MBB, I))
|
|
continue;
|
|
|
|
if (I->isTerminator()) {
|
|
if (searchSuccBBs(MBB, I))
|
|
continue;
|
|
} else if (searchForward(MBB, I)) {
|
|
continue;
|
|
}
|
|
}
|
|
|
|
// Bundle the NOP to the instruction with the delay slot.
|
|
const MipsInstrInfo *TII =
|
|
static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
|
|
BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
|
|
MIBundleBuilder(MBB, I, std::next(I, 2));
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
|
|
/// slots in Mips MachineFunctions
|
|
FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
|
|
return new Filler(tm);
|
|
}
|
|
|
|
template<typename IterTy>
|
|
bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
|
|
RegDefsUses &RegDU, InspectMemInstr& IM,
|
|
IterTy &Filler) const {
|
|
for (IterTy I = Begin; I != End; ++I) {
|
|
// skip debug value
|
|
if (I->isDebugValue())
|
|
continue;
|
|
|
|
if (terminateSearch(*I))
|
|
break;
|
|
|
|
assert((!I->isCall() && !I->isReturn() && !I->isBranch()) &&
|
|
"Cannot put calls, returns or branches in delay slot.");
|
|
|
|
if (delayHasHazard(*I, RegDU, IM))
|
|
continue;
|
|
|
|
if (TM.getSubtarget<MipsSubtarget>().isTargetNaCl()) {
|
|
// In NaCl, instructions that must be masked are forbidden in delay slots.
|
|
// We only check for loads, stores and SP changes. Calls, returns and
|
|
// branches are not checked because non-NaCl targets never put them in
|
|
// delay slots.
|
|
unsigned AddrIdx;
|
|
if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx)
|
|
&& baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg()))
|
|
|| I->modifiesRegister(Mips::SP, TM.getRegisterInfo()))
|
|
continue;
|
|
}
|
|
|
|
Filler = I;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
|
|
if (DisableBackwardSearch)
|
|
return false;
|
|
|
|
RegDefsUses RegDU(TM);
|
|
MemDefsUses MemDU(MBB.getParent()->getFrameInfo());
|
|
ReverseIter Filler;
|
|
|
|
RegDU.init(*Slot);
|
|
|
|
if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Filler))
|
|
return false;
|
|
|
|
MBB.splice(std::next(Slot), &MBB, std::next(Filler).base());
|
|
MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
|
|
++UsefulSlots;
|
|
return true;
|
|
}
|
|
|
|
bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
|
|
// Can handle only calls.
|
|
if (DisableForwardSearch || !Slot->isCall())
|
|
return false;
|
|
|
|
RegDefsUses RegDU(TM);
|
|
NoMemInstr NM;
|
|
Iter Filler;
|
|
|
|
RegDU.setCallerSaved(*Slot);
|
|
|
|
if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Filler))
|
|
return false;
|
|
|
|
MBB.splice(std::next(Slot), &MBB, Filler);
|
|
MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
|
|
++UsefulSlots;
|
|
return true;
|
|
}
|
|
|
|
bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const {
|
|
if (DisableSuccBBSearch)
|
|
return false;
|
|
|
|
MachineBasicBlock *SuccBB = selectSuccBB(MBB);
|
|
|
|
if (!SuccBB)
|
|
return false;
|
|
|
|
RegDefsUses RegDU(TM);
|
|
bool HasMultipleSuccs = false;
|
|
BB2BrMap BrMap;
|
|
std::unique_ptr<InspectMemInstr> IM;
|
|
Iter Filler;
|
|
|
|
// Iterate over SuccBB's predecessor list.
|
|
for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(),
|
|
PE = SuccBB->pred_end(); PI != PE; ++PI)
|
|
if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap))
|
|
return false;
|
|
|
|
// Do not allow moving instructions which have unallocatable register operands
|
|
// across basic block boundaries.
|
|
RegDU.setUnallocatableRegs(*MBB.getParent());
|
|
|
|
// Only allow moving loads from stack or constants if any of the SuccBB's
|
|
// predecessors have multiple successors.
|
|
if (HasMultipleSuccs) {
|
|
IM.reset(new LoadFromStackOrConst());
|
|
} else {
|
|
const MachineFrameInfo *MFI = MBB.getParent()->getFrameInfo();
|
|
IM.reset(new MemDefsUses(MFI));
|
|
}
|
|
|
|
if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Filler))
|
|
return false;
|
|
|
|
insertDelayFiller(Filler, BrMap);
|
|
addLiveInRegs(Filler, *SuccBB);
|
|
Filler->eraseFromParent();
|
|
|
|
return true;
|
|
}
|
|
|
|
MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
|
|
if (B.succ_empty())
|
|
return nullptr;
|
|
|
|
// Select the successor with the larget edge weight.
|
|
auto &Prob = getAnalysis<MachineBranchProbabilityInfo>();
|
|
MachineBasicBlock *S = *std::max_element(B.succ_begin(), B.succ_end(),
|
|
[&](const MachineBasicBlock *Dst0,
|
|
const MachineBasicBlock *Dst1) {
|
|
return Prob.getEdgeWeight(&B, Dst0) < Prob.getEdgeWeight(&B, Dst1);
|
|
});
|
|
return S->isLandingPad() ? nullptr : S;
|
|
}
|
|
|
|
std::pair<MipsInstrInfo::BranchType, MachineInstr *>
|
|
Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
|
|
const MipsInstrInfo *TII =
|
|
static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
|
|
MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr;
|
|
SmallVector<MachineInstr*, 2> BranchInstrs;
|
|
SmallVector<MachineOperand, 2> Cond;
|
|
|
|
MipsInstrInfo::BranchType R =
|
|
TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
|
|
|
|
if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
|
|
return std::make_pair(R, nullptr);
|
|
|
|
if (R != MipsInstrInfo::BT_CondUncond) {
|
|
if (!hasUnoccupiedSlot(BranchInstrs[0]))
|
|
return std::make_pair(MipsInstrInfo::BT_None, nullptr);
|
|
|
|
assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
|
|
|
|
return std::make_pair(R, BranchInstrs[0]);
|
|
}
|
|
|
|
assert((TrueBB == &Dst) || (FalseBB == &Dst));
|
|
|
|
// Examine the conditional branch. See if its slot is occupied.
|
|
if (hasUnoccupiedSlot(BranchInstrs[0]))
|
|
return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]);
|
|
|
|
// If that fails, try the unconditional branch.
|
|
if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
|
|
return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
|
|
|
|
return std::make_pair(MipsInstrInfo::BT_None, nullptr);
|
|
}
|
|
|
|
bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
|
|
RegDefsUses &RegDU, bool &HasMultipleSuccs,
|
|
BB2BrMap &BrMap) const {
|
|
std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
|
|
getBranch(Pred, Succ);
|
|
|
|
// Return if either getBranch wasn't able to analyze the branches or there
|
|
// were no branches with unoccupied slots.
|
|
if (P.first == MipsInstrInfo::BT_None)
|
|
return false;
|
|
|
|
if ((P.first != MipsInstrInfo::BT_Uncond) &&
|
|
(P.first != MipsInstrInfo::BT_NoBranch)) {
|
|
HasMultipleSuccs = true;
|
|
RegDU.addLiveOut(Pred, Succ);
|
|
}
|
|
|
|
BrMap[&Pred] = P.second;
|
|
return true;
|
|
}
|
|
|
|
bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
|
|
InspectMemInstr &IM) const {
|
|
bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill());
|
|
|
|
HasHazard |= IM.hasHazard(Candidate);
|
|
HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
|
|
|
|
return HasHazard;
|
|
}
|
|
|
|
bool Filler::terminateSearch(const MachineInstr &Candidate) const {
|
|
return (Candidate.isTerminator() || Candidate.isCall() ||
|
|
Candidate.isPosition() || Candidate.isInlineAsm() ||
|
|
Candidate.hasUnmodeledSideEffects());
|
|
}
|