mirror of
https://github.com/c64scene-ar/llvm-6502.git
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4da992aeba
mostly based on the ARM AsmParser at this time and is not particularly
functional.
Changed the MBlaze data layout from:
"E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
"E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.
Cleaned up the MBlaze source code:
1. The floating point register class has been removed. The
MicroBlaze does not have floating point registers. Floating
point values are simply stored in integer registers.
2. Renaming the CPURegs register class to GPR to reflect the
standard naming.
3. Removing a lot of stale code from AsmPrinter after
the conversion to InstPrinter.
4. Simplified sign extended loads by marking them as
expanded in ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117054 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
1.9 KiB
Plaintext
33 lines
1.9 KiB
Plaintext
* Writing out ELF files is close to working but the following needs to
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be examined more closely:
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- ELF files are written with the wrong E_MACHINE value because
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ELFObjectWriter::WriteHeader function does not yet support
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target specific E_MACHINE values.
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- ELF relocation records are incorrect because the function
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ELFObjectWriter::RecordRelocation is hard coded for X86/X86-64.
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- Relocations use 2-byte / 4-byte to terminology in reference to
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the size of the immediate value being changed. The Xilinx
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terminology seems to be (???) 4-byte / 8-byte in reference
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to the number of bytes of instructions that are being changed.
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- BRLID and like instructions are always assumed to use a 4-byte
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immediate value for the relocation and BEQID and like instructions
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are always assumed to use a 2-byte immediate value for the relocation.
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I think this means that conditional branches like BEQID can only
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branch += 32768 bytes (~8192 instructions). We should allow conditional
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branches to use 4-byte relocations but I'm not sure how to do that
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right now.
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- Relocation records for indirect calls are not being generated
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correctly. These should emit and IMM 0 directly before the ORI
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instruction that loads the register (just like when a BRLID
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instruction is used instead of an ORI).
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* Code generation seems to work relatively well now but the following
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needs to be examined more closely:
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- The stack layout needs to be examined to make sure it meets
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the standard, especially in regards to var arg functions.
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- The delay slot filler is ad hoc but seems to work. Load and
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store instructions were prevented from being moved to delay
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slots but I'm not sure that is necessary.
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- The processor itineraries are copied from a different backend
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and need to be updated to model the MicroBlaze correctly.
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