mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204618 91177308-0d34-0410-b5e6-96231b3b80d8
1020 lines
36 KiB
C++
1020 lines
36 KiB
C++
//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI Implementation of TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "SIInstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIDefines.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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using namespace llvm;
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SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
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: AMDGPUInstrInfo(tm),
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RI(tm) { }
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//===----------------------------------------------------------------------===//
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// TargetInstrInfo callbacks
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//===----------------------------------------------------------------------===//
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void
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SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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// If we are trying to copy to or from SCC, there is a bug somewhere else in
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// the backend. While it may be theoretically possible to do this, it should
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// never be necessary.
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assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
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static const int16_t Sub0_15[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
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AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
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AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
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};
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static const int16_t Sub0_7[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
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};
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static const int16_t Sub0_3[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
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};
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static const int16_t Sub0_2[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
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};
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static const int16_t Sub0_1[] = {
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AMDGPU::sub0, AMDGPU::sub1, 0
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};
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unsigned Opcode;
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const int16_t *SubIndices;
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if (AMDGPU::M0 == DestReg) {
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// Check if M0 isn't already set to this value
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for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
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I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
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if (!I->definesRegister(AMDGPU::M0))
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continue;
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unsigned Opc = I->getOpcode();
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if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
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break;
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if (!I->readsRegister(SrcReg))
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break;
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// The copy isn't necessary
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return;
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}
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}
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if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_3;
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} else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_7;
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} else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_15;
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} else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
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AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
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AMDGPU::SReg_64RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_1;
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} else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_2;
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} else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
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AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_3;
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} else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
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AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_7;
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} else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
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AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_15;
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} else {
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llvm_unreachable("Can't copy register!");
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}
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while (unsigned SubIdx = *SubIndices++) {
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MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
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get(Opcode), RI.getSubReg(DestReg, SubIdx));
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Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
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if (*SubIndices)
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Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
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}
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}
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unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
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int NewOpc;
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// Try to map original to commuted opcode
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if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
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return NewOpc;
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// Try to map commuted to original opcode
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if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
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return NewOpc;
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return Opcode;
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}
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void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
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DebugLoc DL = MBB.findDebugLoc(MI);
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unsigned KillFlag = isKill ? RegState::Kill : 0;
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if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
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unsigned Lane = MFI->SpillTracker.getNextLane(MRI);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
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MFI->SpillTracker.LaneVGPR)
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.addReg(SrcReg, KillFlag)
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.addImm(Lane);
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MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
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Lane);
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} else {
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for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
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unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), get(AMDGPU::COPY), SubReg)
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.addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
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storeRegToStackSlot(MBB, MI, SubReg, isKill, FrameIndex + i,
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&AMDGPU::SReg_32RegClass, TRI);
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}
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}
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}
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void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
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DebugLoc DL = MBB.findDebugLoc(MI);
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if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) {
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SIMachineFunctionInfo::SpilledReg Spill =
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MFI->SpillTracker.getSpilledReg(FrameIndex);
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assert(Spill.VGPR);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), DestReg)
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.addReg(Spill.VGPR)
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.addImm(Spill.Lane);
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} else {
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for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
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unsigned Flags = RegState::Define;
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if (i == 0) {
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Flags |= RegState::Undef;
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}
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unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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loadRegFromStackSlot(MBB, MI, SubReg, FrameIndex + i,
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&AMDGPU::SReg_32RegClass, TRI);
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BuildMI(MBB, MI, DL, get(AMDGPU::COPY))
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.addReg(DestReg, Flags, RI.getSubRegFromChannel(i))
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.addReg(SubReg);
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}
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}
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}
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MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
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return 0;
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// Cannot commute VOP2 if src0 is SGPR.
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if (isVOP2(MI->getOpcode()) && MI->getOperand(1).isReg() &&
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RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
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return 0;
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if (!MI->getOperand(2).isReg()) {
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// XXX: Commute instructions with FPImm operands
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if (NewMI || MI->getOperand(2).isFPImm() ||
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(!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
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return 0;
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}
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// XXX: Commute VOP3 instructions with abs and neg set.
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if (isVOP3(MI->getOpcode()) &&
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(MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::abs)).getImm() ||
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MI->getOperand(AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::neg)).getImm()))
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return 0;
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unsigned Reg = MI->getOperand(1).getReg();
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unsigned SubReg = MI->getOperand(1).getSubReg();
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MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
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MI->getOperand(2).ChangeToRegister(Reg, false);
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MI->getOperand(2).setSubReg(SubReg);
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} else {
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MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
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}
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if (MI)
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MI->setDesc(get(commuteOpcode(MI->getOpcode())));
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return MI;
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}
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MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg,
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unsigned SrcReg) const {
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return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
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DstReg) .addReg(SrcReg);
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}
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bool SIInstrInfo::isMov(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::S_MOV_B32:
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case AMDGPU::S_MOV_B64:
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::V_MOV_B32_e64:
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return true;
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}
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}
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bool
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SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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return RC != &AMDGPU::EXECRegRegClass;
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}
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namespace llvm {
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namespace AMDGPU {
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// Helper function generated by tablegen. We are wrapping this with
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// an SIInstrInfo function that reutrns bool rather than int.
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int isDS(uint16_t Opcode);
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}
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}
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bool SIInstrInfo::isDS(uint16_t Opcode) const {
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return ::AMDGPU::isDS(Opcode) != -1;
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}
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int SIInstrInfo::isMIMG(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MIMG;
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}
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int SIInstrInfo::isSMRD(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SMRD;
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}
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bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP1;
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}
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bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP2;
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}
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bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP3;
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}
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bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOPC;
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}
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bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
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}
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bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
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union {
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int32_t I;
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float F;
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} Imm;
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if (MO.isImm()) {
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Imm.I = MO.getImm();
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} else if (MO.isFPImm()) {
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Imm.F = MO.getFPImm()->getValueAPF().convertToFloat();
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} else {
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return false;
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}
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// The actual type of the operand does not seem to matter as long
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// as the bits match one of the inline immediate values. For example:
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//
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// -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
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// so it is a legal inline immediate.
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//
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// 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
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// floating-point, so it is a legal inline immediate.
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return (Imm.I >= -16 && Imm.I <= 64) ||
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Imm.F == 0.0f || Imm.F == 0.5f || Imm.F == -0.5f || Imm.F == 1.0f ||
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Imm.F == -1.0f || Imm.F == 2.0f || Imm.F == -2.0f || Imm.F == 4.0f ||
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Imm.F == -4.0f;
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}
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bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
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return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
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}
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bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
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StringRef &ErrInfo) const {
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uint16_t Opcode = MI->getOpcode();
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int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
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int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
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// Make sure the number of operands is correct.
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const MCInstrDesc &Desc = get(Opcode);
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if (!Desc.isVariadic() &&
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Desc.getNumOperands() != MI->getNumExplicitOperands()) {
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ErrInfo = "Instruction has wrong number of operands.";
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return false;
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}
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// Make sure the register classes are correct
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for (unsigned i = 0, e = Desc.getNumOperands(); i != e; ++i) {
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switch (Desc.OpInfo[i].OperandType) {
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case MCOI::OPERAND_REGISTER:
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break;
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case MCOI::OPERAND_IMMEDIATE:
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if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm()) {
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ErrInfo = "Expected immediate, but got non-immediate";
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return false;
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}
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// Fall-through
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default:
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continue;
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}
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if (!MI->getOperand(i).isReg())
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continue;
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int RegClass = Desc.OpInfo[i].RegClass;
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if (RegClass != -1) {
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unsigned Reg = MI->getOperand(i).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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const TargetRegisterClass *RC = RI.getRegClass(RegClass);
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if (!RC->contains(Reg)) {
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ErrInfo = "Operand has incorrect register class.";
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return false;
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}
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}
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}
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// Verify VOP*
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if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
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unsigned ConstantBusCount = 0;
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unsigned SGPRUsed = AMDGPU::NoRegister;
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for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() &&
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!TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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// EXEC register uses the constant bus.
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if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
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++ConstantBusCount;
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// SGPRs use the constant bus
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if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
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(!MO.isImplicit() &&
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(AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
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AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
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if (SGPRUsed != MO.getReg()) {
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++ConstantBusCount;
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SGPRUsed = MO.getReg();
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}
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}
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}
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// Literal constants use the constant bus.
|
|
if (isLiteralConstant(MO))
|
|
++ConstantBusCount;
|
|
}
|
|
if (ConstantBusCount > 1) {
|
|
ErrInfo = "VOP* instruction uses the constant bus more than once";
|
|
return false;
|
|
}
|
|
}
|
|
|
|
// Verify SRC1 for VOP2 and VOPC
|
|
if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
|
|
const MachineOperand &Src1 = MI->getOperand(Src1Idx);
|
|
if (Src1.isImm() || Src1.isFPImm()) {
|
|
ErrInfo = "VOP[2C] src1 cannot be an immediate.";
|
|
return false;
|
|
}
|
|
}
|
|
|
|
// Verify VOP3
|
|
if (isVOP3(Opcode)) {
|
|
if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
|
|
ErrInfo = "VOP3 src0 cannot be a literal constant.";
|
|
return false;
|
|
}
|
|
if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
|
|
ErrInfo = "VOP3 src1 cannot be a literal constant.";
|
|
return false;
|
|
}
|
|
if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
|
|
ErrInfo = "VOP3 src2 cannot be a literal constant.";
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
|
|
switch (MI.getOpcode()) {
|
|
default: return AMDGPU::INSTRUCTION_LIST_END;
|
|
case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
|
|
case AMDGPU::COPY: return AMDGPU::COPY;
|
|
case AMDGPU::PHI: return AMDGPU::PHI;
|
|
case AMDGPU::S_MOV_B32:
|
|
return MI.getOperand(1).isReg() ?
|
|
AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
|
|
case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
|
|
case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
|
|
case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
|
|
case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
|
|
case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
|
|
case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
|
|
case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
|
|
case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
|
|
case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
|
|
case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
|
|
case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
|
|
case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
|
|
case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
|
|
case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
|
|
case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
|
|
case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
|
|
case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
|
|
}
|
|
}
|
|
|
|
bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
|
|
return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
|
|
}
|
|
|
|
const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
|
|
unsigned OpNo) const {
|
|
const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
|
|
const MCInstrDesc &Desc = get(MI.getOpcode());
|
|
if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
|
|
Desc.OpInfo[OpNo].RegClass == -1)
|
|
return MRI.getRegClass(MI.getOperand(OpNo).getReg());
|
|
|
|
unsigned RCID = Desc.OpInfo[OpNo].RegClass;
|
|
return RI.getRegClass(RCID);
|
|
}
|
|
|
|
bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
|
|
switch (MI.getOpcode()) {
|
|
case AMDGPU::COPY:
|
|
case AMDGPU::REG_SEQUENCE:
|
|
return RI.hasVGPRs(getOpRegClass(MI, 0));
|
|
default:
|
|
return RI.hasVGPRs(getOpRegClass(MI, OpNo));
|
|
}
|
|
}
|
|
|
|
void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
|
|
MachineBasicBlock::iterator I = MI;
|
|
MachineOperand &MO = MI->getOperand(OpIdx);
|
|
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
|
|
unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
|
|
const TargetRegisterClass *RC = RI.getRegClass(RCID);
|
|
unsigned Opcode = AMDGPU::V_MOV_B32_e32;
|
|
if (MO.isReg()) {
|
|
Opcode = AMDGPU::COPY;
|
|
} else if (RI.isSGPRClass(RC)) {
|
|
Opcode = AMDGPU::S_MOV_B32;
|
|
}
|
|
|
|
const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
|
|
unsigned Reg = MRI.createVirtualRegister(VRC);
|
|
BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
|
|
Reg).addOperand(MO);
|
|
MO.ChangeToRegister(Reg, false);
|
|
}
|
|
|
|
unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
|
|
MachineRegisterInfo &MRI,
|
|
MachineOperand &SuperReg,
|
|
const TargetRegisterClass *SuperRC,
|
|
unsigned SubIdx,
|
|
const TargetRegisterClass *SubRC)
|
|
const {
|
|
assert(SuperReg.isReg());
|
|
|
|
unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
|
|
unsigned SubReg = MRI.createVirtualRegister(SubRC);
|
|
|
|
// Just in case the super register is itself a sub-register, copy it to a new
|
|
// value so we don't need to wory about merging its subreg index with the
|
|
// SubIdx passed to this function. The register coalescer should be able to
|
|
// eliminate this extra copy.
|
|
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
|
|
NewSuperReg)
|
|
.addOperand(SuperReg);
|
|
|
|
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
|
|
SubReg)
|
|
.addReg(NewSuperReg, 0, SubIdx);
|
|
return SubReg;
|
|
}
|
|
|
|
void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
|
|
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
|
|
int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
|
|
AMDGPU::OpName::src0);
|
|
int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
|
|
AMDGPU::OpName::src1);
|
|
int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
|
|
AMDGPU::OpName::src2);
|
|
|
|
// Legalize VOP2
|
|
if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
|
|
MachineOperand &Src0 = MI->getOperand(Src0Idx);
|
|
MachineOperand &Src1 = MI->getOperand(Src1Idx);
|
|
|
|
// If the instruction implicitly reads VCC, we can't have any SGPR operands,
|
|
// so move any.
|
|
bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI);
|
|
if (ReadsVCC && Src0.isReg() &&
|
|
RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {
|
|
legalizeOpWithMove(MI, Src0Idx);
|
|
return;
|
|
}
|
|
|
|
if (ReadsVCC && Src1.isReg() &&
|
|
RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
|
|
legalizeOpWithMove(MI, Src1Idx);
|
|
return;
|
|
}
|
|
|
|
// Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must
|
|
// be the first operand, and there can only be one.
|
|
if (Src1.isImm() || Src1.isFPImm() ||
|
|
(Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {
|
|
if (MI->isCommutable()) {
|
|
if (commuteInstruction(MI))
|
|
return;
|
|
}
|
|
legalizeOpWithMove(MI, Src1Idx);
|
|
}
|
|
}
|
|
|
|
// XXX - Do any VOP3 instructions read VCC?
|
|
// Legalize VOP3
|
|
if (isVOP3(MI->getOpcode())) {
|
|
int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
|
|
unsigned SGPRReg = AMDGPU::NoRegister;
|
|
for (unsigned i = 0; i < 3; ++i) {
|
|
int Idx = VOP3Idx[i];
|
|
if (Idx == -1)
|
|
continue;
|
|
MachineOperand &MO = MI->getOperand(Idx);
|
|
|
|
if (MO.isReg()) {
|
|
if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
|
|
continue; // VGPRs are legal
|
|
|
|
assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
|
|
|
|
if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
|
|
SGPRReg = MO.getReg();
|
|
// We can use one SGPR in each VOP3 instruction.
|
|
continue;
|
|
}
|
|
} else if (!isLiteralConstant(MO)) {
|
|
// If it is not a register and not a literal constant, then it must be
|
|
// an inline constant which is always legal.
|
|
continue;
|
|
}
|
|
// If we make it this far, then the operand is not legal and we must
|
|
// legalize it.
|
|
legalizeOpWithMove(MI, Idx);
|
|
}
|
|
}
|
|
|
|
// Legalize REG_SEQUENCE
|
|
// The register class of the operands much be the same type as the register
|
|
// class of the output.
|
|
if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
|
|
const TargetRegisterClass *RC = NULL, *SRC = NULL, *VRC = NULL;
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
|
|
if (!MI->getOperand(i).isReg() ||
|
|
!TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
|
|
continue;
|
|
const TargetRegisterClass *OpRC =
|
|
MRI.getRegClass(MI->getOperand(i).getReg());
|
|
if (RI.hasVGPRs(OpRC)) {
|
|
VRC = OpRC;
|
|
} else {
|
|
SRC = OpRC;
|
|
}
|
|
}
|
|
|
|
// If any of the operands are VGPR registers, then they all most be
|
|
// otherwise we will create illegal VGPR->SGPR copies when legalizing
|
|
// them.
|
|
if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
|
|
if (!VRC) {
|
|
assert(SRC);
|
|
VRC = RI.getEquivalentVGPRClass(SRC);
|
|
}
|
|
RC = VRC;
|
|
} else {
|
|
RC = SRC;
|
|
}
|
|
|
|
// Update all the operands so they have the same type.
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
|
|
if (!MI->getOperand(i).isReg() ||
|
|
!TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
|
|
continue;
|
|
unsigned DstReg = MRI.createVirtualRegister(RC);
|
|
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
get(AMDGPU::COPY), DstReg)
|
|
.addOperand(MI->getOperand(i));
|
|
MI->getOperand(i).setReg(DstReg);
|
|
}
|
|
}
|
|
|
|
// Legalize MUBUF* instructions
|
|
// FIXME: If we start using the non-addr64 instructions for compute, we
|
|
// may need to legalize them here.
|
|
|
|
int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
|
|
AMDGPU::OpName::srsrc);
|
|
int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
|
|
AMDGPU::OpName::vaddr);
|
|
if (SRsrcIdx != -1 && VAddrIdx != -1) {
|
|
const TargetRegisterClass *VAddrRC =
|
|
RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
|
|
|
|
if(VAddrRC->getSize() == 8 &&
|
|
MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
|
|
// We have a MUBUF instruction that uses a 64-bit vaddr register and
|
|
// srsrc has the incorrect register class. In order to fix this, we
|
|
// need to extract the pointer from the resource descriptor (srsrc),
|
|
// add it to the value of vadd, then store the result in the vaddr
|
|
// operand. Then, we need to set the pointer field of the resource
|
|
// descriptor to zero.
|
|
|
|
MachineBasicBlock &MBB = *MI->getParent();
|
|
MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
|
|
MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
|
|
unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
|
|
unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
|
|
unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
|
|
unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
|
|
unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
|
|
unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
|
|
unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
|
|
unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
|
|
|
|
// SRsrcPtrLo = srsrc:sub0
|
|
SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
|
|
&AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
|
|
|
|
// SRsrcPtrHi = srsrc:sub1
|
|
SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
|
|
&AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
|
|
|
|
// VAddrLo = vaddr:sub0
|
|
VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
|
|
&AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
|
|
|
|
// VAddrHi = vaddr:sub1
|
|
VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
|
|
&AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
|
|
|
|
// NewVaddrLo = SRsrcPtrLo + VAddrLo
|
|
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
|
|
NewVAddrLo)
|
|
.addReg(SRsrcPtrLo)
|
|
.addReg(VAddrLo)
|
|
.addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
|
|
|
|
// NewVaddrHi = SRsrcPtrHi + VAddrHi
|
|
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
|
|
NewVAddrHi)
|
|
.addReg(SRsrcPtrHi)
|
|
.addReg(VAddrHi)
|
|
.addReg(AMDGPU::VCC, RegState::ImplicitDefine)
|
|
.addReg(AMDGPU::VCC, RegState::Implicit);
|
|
|
|
// NewVaddr = {NewVaddrHi, NewVaddrLo}
|
|
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
|
|
NewVAddr)
|
|
.addReg(NewVAddrLo)
|
|
.addImm(AMDGPU::sub0)
|
|
.addReg(NewVAddrHi)
|
|
.addImm(AMDGPU::sub1);
|
|
|
|
// Zero64 = 0
|
|
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
|
|
Zero64)
|
|
.addImm(0);
|
|
|
|
// SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
|
|
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
|
|
SRsrcFormatLo)
|
|
.addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
|
|
|
|
// SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
|
|
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
|
|
SRsrcFormatHi)
|
|
.addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
|
|
|
|
// NewSRsrc = {Zero64, SRsrcFormat}
|
|
BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
|
|
NewSRsrc)
|
|
.addReg(Zero64)
|
|
.addImm(AMDGPU::sub0_sub1)
|
|
.addReg(SRsrcFormatLo)
|
|
.addImm(AMDGPU::sub2)
|
|
.addReg(SRsrcFormatHi)
|
|
.addImm(AMDGPU::sub3);
|
|
|
|
// Update the instruction to use NewVaddr
|
|
MI->getOperand(VAddrIdx).setReg(NewVAddr);
|
|
// Update the instruction to use NewSRsrc
|
|
MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
|
|
}
|
|
}
|
|
}
|
|
|
|
void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
|
|
SmallVector<MachineInstr *, 128> Worklist;
|
|
Worklist.push_back(&TopInst);
|
|
|
|
while (!Worklist.empty()) {
|
|
MachineInstr *Inst = Worklist.pop_back_val();
|
|
MachineBasicBlock *MBB = Inst->getParent();
|
|
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
|
|
|
|
// Handle some special cases
|
|
switch(Inst->getOpcode()) {
|
|
case AMDGPU::S_MOV_B64: {
|
|
DebugLoc DL = Inst->getDebugLoc();
|
|
|
|
// If the source operand is a register we can replace this with a
|
|
// copy
|
|
if (Inst->getOperand(1).isReg()) {
|
|
MachineInstr *Copy = BuildMI(*MBB, Inst, DL,
|
|
get(TargetOpcode::COPY))
|
|
.addOperand(Inst->getOperand(0))
|
|
.addOperand(Inst->getOperand(1));
|
|
Worklist.push_back(Copy);
|
|
} else {
|
|
// Otherwise, we need to split this into two movs, because there is
|
|
// no 64-bit VALU move instruction.
|
|
unsigned LoDst, HiDst, Dst;
|
|
LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
|
|
HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
|
|
Dst = MRI.createVirtualRegister(
|
|
MRI.getRegClass(Inst->getOperand(0).getReg()));
|
|
|
|
MachineInstr *Lo = BuildMI(*MBB, Inst, DL, get(AMDGPU::S_MOV_B32),
|
|
LoDst)
|
|
.addImm(Inst->getOperand(1).getImm() & 0xFFFFFFFF);
|
|
MachineInstr *Hi = BuildMI(*MBB, Inst, DL, get(AMDGPU::S_MOV_B32),
|
|
HiDst)
|
|
.addImm(Inst->getOperand(1).getImm() >> 32);
|
|
|
|
BuildMI(*MBB, Inst, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
|
|
.addReg(LoDst)
|
|
.addImm(AMDGPU::sub0)
|
|
.addReg(HiDst)
|
|
.addImm(AMDGPU::sub1);
|
|
|
|
MRI.replaceRegWith(Inst->getOperand(0).getReg(), Dst);
|
|
Worklist.push_back(Lo);
|
|
Worklist.push_back(Hi);
|
|
}
|
|
Inst->eraseFromParent();
|
|
continue;
|
|
}
|
|
}
|
|
|
|
unsigned NewOpcode = getVALUOp(*Inst);
|
|
if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
|
|
// We cannot move this instruction to the VALU, so we should try to
|
|
// legalize its operands instead.
|
|
legalizeOperands(Inst);
|
|
continue;
|
|
}
|
|
|
|
// Use the new VALU Opcode.
|
|
const MCInstrDesc &NewDesc = get(NewOpcode);
|
|
Inst->setDesc(NewDesc);
|
|
|
|
// Remove any references to SCC. Vector instructions can't read from it, and
|
|
// We're just about to add the implicit use / defs of VCC, and we don't want
|
|
// both.
|
|
for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
|
|
MachineOperand &Op = Inst->getOperand(i);
|
|
if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
|
|
Inst->RemoveOperand(i);
|
|
}
|
|
|
|
// Add the implict and explicit register definitions.
|
|
if (NewDesc.ImplicitUses) {
|
|
for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
|
|
unsigned Reg = NewDesc.ImplicitUses[i];
|
|
Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
|
|
}
|
|
}
|
|
|
|
if (NewDesc.ImplicitDefs) {
|
|
for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
|
|
unsigned Reg = NewDesc.ImplicitDefs[i];
|
|
Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
|
|
}
|
|
}
|
|
|
|
legalizeOperands(Inst);
|
|
|
|
// Update the destination register class.
|
|
const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
|
|
|
|
switch (Inst->getOpcode()) {
|
|
// For target instructions, getOpRegClass just returns the virtual
|
|
// register class associated with the operand, so we need to find an
|
|
// equivalent VGPR register class in order to move the instruction to the
|
|
// VALU.
|
|
case AMDGPU::COPY:
|
|
case AMDGPU::PHI:
|
|
case AMDGPU::REG_SEQUENCE:
|
|
if (RI.hasVGPRs(NewDstRC))
|
|
continue;
|
|
NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
|
|
if (!NewDstRC)
|
|
continue;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
unsigned DstReg = Inst->getOperand(0).getReg();
|
|
unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
|
|
MRI.replaceRegWith(DstReg, NewDstReg);
|
|
|
|
for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
|
|
E = MRI.use_end(); I != E; ++I) {
|
|
MachineInstr &UseMI = *I->getParent();
|
|
if (!canReadVGPR(UseMI, I.getOperandNo())) {
|
|
Worklist.push_back(&UseMI);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Indirect addressing callbacks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
|
|
unsigned Channel) const {
|
|
assert(Channel == 0);
|
|
return RegIndex;
|
|
}
|
|
|
|
const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
|
|
return &AMDGPU::VReg_32RegClass;
|
|
}
|
|
|
|
MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
|
|
MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned ValueReg,
|
|
unsigned Address, unsigned OffsetReg) const {
|
|
const DebugLoc &DL = MBB->findDebugLoc(I);
|
|
unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
|
|
getIndirectIndexBegin(*MBB->getParent()));
|
|
|
|
return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
|
|
.addReg(IndirectBaseReg, RegState::Define)
|
|
.addOperand(I->getOperand(0))
|
|
.addReg(IndirectBaseReg)
|
|
.addReg(OffsetReg)
|
|
.addImm(0)
|
|
.addReg(ValueReg);
|
|
}
|
|
|
|
MachineInstrBuilder SIInstrInfo::buildIndirectRead(
|
|
MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned ValueReg,
|
|
unsigned Address, unsigned OffsetReg) const {
|
|
const DebugLoc &DL = MBB->findDebugLoc(I);
|
|
unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
|
|
getIndirectIndexBegin(*MBB->getParent()));
|
|
|
|
return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
|
|
.addOperand(I->getOperand(0))
|
|
.addOperand(I->getOperand(1))
|
|
.addReg(IndirectBaseReg)
|
|
.addReg(OffsetReg)
|
|
.addImm(0);
|
|
|
|
}
|
|
|
|
void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
|
|
const MachineFunction &MF) const {
|
|
int End = getIndirectIndexEnd(MF);
|
|
int Begin = getIndirectIndexBegin(MF);
|
|
|
|
if (End == -1)
|
|
return;
|
|
|
|
|
|
for (int Index = Begin; Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
|
|
|
|
for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
|
|
Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
|
|
}
|