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llvm-6502/lib/Target/R600
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Tom Stellard b07ec96068 Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions" 
This reverts commit a6a39ced09.
This is the wrong version of this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188523 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 01:18:43 +00:00
..
InstPrinter
MCTargetDesc
TargetInfo
AMDGPU.h R600/SI: Convert v16i8 resource descriptors to i128 2013-08-14 23:24:45 +00:00
AMDGPU.td
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td R600/SI: Fix an obvious typo 2013-08-14 22:22:03 +00:00
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUIndirectAddressing.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td R600: Add support for i16 and i8 global stores 2013-08-16 01:12:06 +00:00
AMDGPUInstructions.td R600: Add support for i16 and i8 global stores 2013-08-16 01:12:06 +00:00
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp R600: Enable folding of inline literals into REQ_SEQUENCE instructions 2013-08-16 01:11:55 +00:00
AMDGPUISelLowering.cpp R600: Add support for global vector loads with element types less than 32-bits 2013-08-16 01:12:16 +00:00
AMDGPUISelLowering.h R600: Add support for global vector stores with elements less than 32-bits 2013-08-16 01:12:11 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.h R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp R600/SI: Convert v16i8 resource descriptors to i128 2013-08-14 23:24:45 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILBase.td
AMDILCFGStructurizer.cpp
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td
AMDILISelLowering.cpp
AMDILRegisterInfo.td
CMakeLists.txt R600/SI: Convert v16i8 resource descriptors to i128 2013-08-14 23:24:45 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600ControlFlowFinalizer.cpp R600: Add IsExport bit to TableGen instruction definitions 2013-08-16 01:11:51 +00:00
R600Defines.h R600: Add IsExport bit to TableGen instruction definitions 2013-08-16 01:11:51 +00:00
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td R600: Add IsExport bit to TableGen instruction definitions 2013-08-16 01:11:51 +00:00
R600InstrInfo.cpp R600: Add IsExport bit to TableGen instruction definitions 2013-08-16 01:11:51 +00:00
R600InstrInfo.h R600: Add IsExport bit to TableGen instruction definitions 2013-08-16 01:11:51 +00:00
R600Instructions.td R600: Add support for i16 and i8 global stores 2013-08-16 01:12:06 +00:00
R600Intrinsics.td
R600ISelLowering.cpp R600: Add support for global vector stores with elements less than 32-bits 2013-08-16 01:12:11 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
R600MachineScheduler.h Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
R600OptimizeVectorRegisters.cpp R600: Enable folding of inline literals into REQ_SEQUENCE instructions 2013-08-16 01:11:55 +00:00
R600Packetizer.cpp Revert "R600: Non vector only instruction can be scheduled on trans unit" 2013-07-31 20:43:27 +00:00
R600RegisterInfo.cpp R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 2013-08-14 23:24:32 +00:00
R600RegisterInfo.h R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 2013-08-14 23:24:32 +00:00
R600RegisterInfo.td R600: Add 64-bit float load/store support 2013-08-01 15:23:42 +00:00
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp Fix spelling 2013-08-15 23:11:03 +00:00
SIAnnotateControlFlow.cpp
SIDefines.h R600/SI: Assign a register class to the $vaddr operand for MIMG instructions 2013-08-14 23:24:17 +00:00
SIFixSGPRCopies.cpp R600/SI: Use VSrc_* register classes as the default classes for types 2013-08-06 23:08:28 +00:00
SIInsertWaits.cpp Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions" 2013-08-16 01:18:43 +00:00
SIInstrFormats.td R600/SI: Assign a register class to the $vaddr operand for MIMG instructions 2013-08-14 23:24:17 +00:00
SIInstrInfo.cpp R600/SI: Assign a register class to the $vaddr operand for MIMG instructions 2013-08-14 23:24:17 +00:00
SIInstrInfo.h R600/SI: Assign a register class to the $vaddr operand for MIMG instructions 2013-08-14 23:24:17 +00:00
SIInstrInfo.td Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions" 2013-08-16 01:18:43 +00:00
SIInstructions.td Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions" 2013-08-16 01:18:43 +00:00
SIIntrinsics.td R600/SI: Convert v16i8 resource descriptors to i128 2013-08-14 23:24:45 +00:00
SIISelLowering.cpp R600/SI: Improve legalization of vector operations 2013-08-14 23:25:00 +00:00
SIISelLowering.h R600/SI: Improve legalization of vector operations 2013-08-14 23:25:00 +00:00
SILowerControlFlow.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp R600/SI: Choose the correct MOV instruction for copying immediates 2013-08-14 23:24:24 +00:00
SIRegisterInfo.h R600/SI: Choose the correct MOV instruction for copying immediates 2013-08-14 23:24:24 +00:00
SIRegisterInfo.td R600/SI: Convert v16i8 resource descriptors to i128 2013-08-14 23:24:45 +00:00
SISchedule.td
SITypeRewriter.cpp R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics 2013-08-14 23:24:53 +00:00