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This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
149 lines
5.3 KiB
C++
149 lines
5.3 KiB
C++
//===-- ARM64CleanupLocalDynamicTLSPass.cpp -----------------------*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Local-dynamic access to thread-local variables proceeds in three stages.
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//
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// 1. The offset of this Module's thread-local area from TPIDR_EL0 is calculated
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// in much the same way as a general-dynamic TLS-descriptor access against
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// the special symbol _TLS_MODULE_BASE.
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// 2. The variable's offset from _TLS_MODULE_BASE_ is calculated using
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// instructions with "dtprel" modifiers.
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// 3. These two are added, together with TPIDR_EL0, to obtain the variable's
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// true address.
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//
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// This is only better than general-dynamic access to the variable if two or
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// more of the first stage TLS-descriptor calculations can be combined. This
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// pass looks through a function and performs such combinations.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM64.h"
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#include "ARM64InstrInfo.h"
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#include "ARM64MachineFunctionInfo.h"
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#include "ARM64TargetMachine.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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namespace {
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struct LDTLSCleanup : public MachineFunctionPass {
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static char ID;
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LDTLSCleanup() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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ARM64FunctionInfo *AFI = MF.getInfo<ARM64FunctionInfo>();
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if (AFI->getNumLocalDynamicTLSAccesses() < 2) {
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// No point folding accesses if there isn't at least two.
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return false;
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}
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MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
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return VisitNode(DT->getRootNode(), 0);
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}
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// Visit the dominator subtree rooted at Node in pre-order.
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// If TLSBaseAddrReg is non-null, then use that to replace any
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// TLS_base_addr instructions. Otherwise, create the register
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// when the first such instruction is seen, and then use it
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// as we encounter more instructions.
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bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
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MachineBasicBlock *BB = Node->getBlock();
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bool Changed = false;
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// Traverse the current block.
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for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
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++I) {
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switch (I->getOpcode()) {
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case ARM64::TLSDESC_BLR:
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// Make sure it's a local dynamic access.
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if (!I->getOperand(1).isSymbol() ||
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strcmp(I->getOperand(1).getSymbolName(), "_TLS_MODULE_BASE_"))
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break;
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if (TLSBaseAddrReg)
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I = replaceTLSBaseAddrCall(I, TLSBaseAddrReg);
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else
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I = setRegister(I, &TLSBaseAddrReg);
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Changed = true;
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break;
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default:
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break;
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}
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}
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// Visit the children of this block in the dominator tree.
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for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
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I != E; ++I) {
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Changed |= VisitNode(*I, TLSBaseAddrReg);
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}
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return Changed;
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}
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// Replace the TLS_base_addr instruction I with a copy from
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// TLSBaseAddrReg, returning the new instruction.
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MachineInstr *replaceTLSBaseAddrCall(MachineInstr *I,
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unsigned TLSBaseAddrReg) {
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MachineFunction *MF = I->getParent()->getParent();
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const ARM64TargetMachine *TM =
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static_cast<const ARM64TargetMachine *>(&MF->getTarget());
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const ARM64InstrInfo *TII = TM->getInstrInfo();
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// Insert a Copy from TLSBaseAddrReg to x0, which is where the rest of the
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// code sequence assumes the address will be.
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MachineInstr *Copy =
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BuildMI(*I->getParent(), I, I->getDebugLoc(),
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TII->get(TargetOpcode::COPY), ARM64::X0).addReg(TLSBaseAddrReg);
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// Erase the TLS_base_addr instruction.
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I->eraseFromParent();
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return Copy;
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}
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// Create a virtal register in *TLSBaseAddrReg, and populate it by
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// inserting a copy instruction after I. Returns the new instruction.
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MachineInstr *setRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
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MachineFunction *MF = I->getParent()->getParent();
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const ARM64TargetMachine *TM =
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static_cast<const ARM64TargetMachine *>(&MF->getTarget());
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const ARM64InstrInfo *TII = TM->getInstrInfo();
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// Create a virtual register for the TLS base address.
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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*TLSBaseAddrReg = RegInfo.createVirtualRegister(&ARM64::GPR64RegClass);
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// Insert a copy from X0 to TLSBaseAddrReg for later.
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MachineInstr *Next = I->getNextNode();
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MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
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TII->get(TargetOpcode::COPY),
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*TLSBaseAddrReg).addReg(ARM64::X0);
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return Copy;
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}
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virtual const char *getPassName() const {
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return "Local Dynamic TLS Access Clean-up";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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char LDTLSCleanup::ID = 0;
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FunctionPass *llvm::createARM64CleanupLocalDynamicTLSPass() {
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return new LDTLSCleanup();
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}
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