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e502a6aad3
This implements the unwind_raw directive for the ARM IAS. The unwind_raw directive takes the form of a stack offset value followed by one or more bytes representing the opcodes to be emitted. The opcode emitted will interpreted as if it were assembled by the opcode assembler via the standard unwinding directives. Thanks to Logan Chien for an extra test! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199707 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.4 KiB
C++
95 lines
2.4 KiB
C++
//===-- ARMUnwindOpAsm.h - ARM Unwind Opcodes Assembler ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the unwind opcode assmebler for ARM exception handling
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// table.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARM_UNWIND_OP_ASM_H
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#define ARM_UNWIND_OP_ASM_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/ARMEHABI.h"
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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class MCSymbol;
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class UnwindOpcodeAssembler {
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private:
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llvm::SmallVector<uint8_t, 32> Ops;
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llvm::SmallVector<unsigned, 8> OpBegins;
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bool HasPersonality;
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public:
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UnwindOpcodeAssembler()
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: HasPersonality(0) {
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OpBegins.push_back(0);
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}
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/// Reset the unwind opcode assembler.
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void Reset() {
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Ops.clear();
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OpBegins.clear();
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OpBegins.push_back(0);
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HasPersonality = 0;
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}
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/// Set the personality
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void setPersonality(const MCSymbol *Per) {
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HasPersonality = 1;
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}
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/// Emit unwind opcodes for .save directives
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void EmitRegSave(uint32_t RegSave);
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/// Emit unwind opcodes for .vsave directives
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void EmitVFPRegSave(uint32_t VFPRegSave);
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/// Emit unwind opcodes to copy address from source register to $sp.
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void EmitSetSP(uint16_t Reg);
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/// Emit unwind opcodes to add $sp with an offset.
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void EmitSPOffset(int64_t Offset);
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/// Emit unwind raw opcodes
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void EmitRaw(const SmallVectorImpl<uint8_t> &Opcodes) {
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Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end());
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OpBegins.push_back(OpBegins.back() + Opcodes.size());
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}
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/// Finalize the unwind opcode sequence for EmitBytes()
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void Finalize(unsigned &PersonalityIndex,
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SmallVectorImpl<uint8_t> &Result);
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private:
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void EmitInt8(unsigned Opcode) {
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Ops.push_back(Opcode & 0xff);
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OpBegins.push_back(OpBegins.back() + 1);
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}
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void EmitInt16(unsigned Opcode) {
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Ops.push_back((Opcode >> 8) & 0xff);
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Ops.push_back(Opcode & 0xff);
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OpBegins.push_back(OpBegins.back() + 2);
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}
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void EmitBytes(const uint8_t *Opcode, size_t Size) {
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Ops.insert(Ops.end(), Opcode, Opcode + Size);
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OpBegins.push_back(OpBegins.back() + Size);
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}
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};
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} // namespace llvm
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#endif // ARM_UNWIND_OP_ASM_H
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